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KSZ8091MNXIA-TR

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Microchip Tech Ethernet ICs, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ksz8091mnxia-trfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Contents

README

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KSZ8091MNXIA-TR

Microchip Tech · Ethernet ICs · QFN-32-EP(5x5)

KSZ8091MNXIA-TR from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground.
2 VDD_1.2 power_out 1.2V core VDD supplied by the KSZ8091MNX itself; decouple with 2.2 µF and 0.1 µF capacitors to ground.
3 VDDA_3.3 power_in 3.3V analog VDD; connect to the board 3.3V supply through a ferrite bead and decouple with 22 µF and 0.1 µF capacitors to ground.
4 RXM bidirectional Physical receive or transmit signal (- differential).
5 RXP bidirectional Physical receive or transmit signal (+ differential).
6 TXM bidirectional Physical transmit or receive signal (- differential).
7 TXP bidirectional Physical transmit or receive signal (+ differential).
8 XO output Crystal feedback for 25 MHz crystal; no connect if an oscillator or external clock source is used.
9 XI input Crystal/oscillator/external clock input, 25 MHz ±50 ppm.
10 REXT input Sets PHY transmit output current; connect a 6.49 kΩ resistor to ground.
11 MDIO bidirectional Management interface (MII) data I/O with weak pull-up, open-drain, requires an external 1.0 kΩ pull-up resistor.
12 MDC input Management interface (MII) clock input with internal pull-up, synchronous to MDIO.
13 RXD3/PHYAD0 bidirectional MII receive data output [3]; at reset de-assertion the strap value is latched as PHYADDR[0] (internal pull-up).
14 RXD2/PHYAD1 bidirectional MII receive data output [2]; at reset de-assertion the strap value is latched as PHYADDR[1] (internal pull-down).
15 RXD1/PHYAD2 bidirectional MII receive data output [1]; at reset de-assertion the strap value is latched as PHYADDR[2] (internal pull-down).
16 RXD0/DUPLEX bidirectional MII receive data output [0]; at reset de-assertion the strap value is latched as DUPLEX (internal pull-up, default half-duplex).
17 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD; decouple with 22 µF and 0.1 µF capacitors to ground.
18 RXDV/CONFIG2 bidirectional MII receive data valid output; at reset de-assertion the strap value is latched as CONFIG2 (internal pull-down).
19 RXC/B-CAST_OFF bidirectional MII receive clock output; at reset de-assertion the strap value is latched as B-CAST_OFF (internal pull-down).
20 RXER/ISO bidirectional MII receive error output; at reset de-assertion the strap value is latched as ISOLATE (internal pull-down).
21 INTRP/PME_N2/NAND_TREE# bidirectional Programmable open-drain interrupt or PME_N (option 2) output with weak pull-up, requiring an external 1.0 kΩ pull-up to VDDIO; latched as NAND Tree# at reset de-assertion.
22 TXC/PME_EN bidirectional MII transmit clock output (no connection in MII back-to-back mode); at reset de-assertion the strap value is latched as PME_EN (internal pull-down).
23 TXEN input MII transmit enable input.
24 TXD0 input MII transmit data input [0].
25 TXD1 input MII transmit data input [1].
26 TXD2 input MII transmit data input [2].
27 TXD3 input MII transmit data input [3].
28 COL/CONFIG0 bidirectional MII collision detect output; at reset de-assertion the strap value is latched as CONFIG0 (internal pull-down).
29 CRS/CONFIG1 bidirectional MII carrier sense output; at reset de-assertion the strap value is latched as CONFIG1 (internal pull-down).
30 LED0/PME_N1/NWAYEN bidirectional Programmable LED0 or PME_N (option 1, open-drain, requires external 1.0 kΩ pull-up to VDDIO) output; latched as auto-negotiation enable at reset de-assertion (internal pull-up).
31 TXER input MII transmit error input with internal pull-down; can be left unconnected in non-EEE mode and should be pulled high for NAND Tree testing.
32 RST# input Chip reset, active low, with internal pull-up.
33 PADDLE passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-32-EP(5x5)
Category Communication Interface Chip/UART/485/232
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input High Voltage VIH 2 V VDDIO = 3.3V 58
Input High Voltage VIH 1.8 V VDDIO = 2.5V 58
Input High Voltage VIH 1.3 V VDDIO = 1.8V 58
Input Low Voltage VIL 0.8 V VDDIO = 3.3V 58
Input Low Voltage VIL 0.7 V VDDIO = 2.5V 58
Input Low Voltage VIL 0.5 V VDDIO = 1.8V 58
Input Current /IIN/ 10 μA VIN = GND ~ VDDIO 58
Output High Voltage VOH 2.4 V VDDIO = 3.3V 58
Output High Voltage VOH 2 V VDDIO = 2.5V 58
Output High Voltage VOH 1.5 V VDDIO = 1.8V 58
Output Low Voltage VOL 0.4 V VDDIO = 3.3V 58
Output Low Voltage VOL 0.3 V VDDIO = 1.8V 58
Output Tri-State Leakage /IOZ/ 10 μA 58
Internal Pull-Up Resistance pu 30 45 73 kΩ VDDIO = 3.3V 58
Internal Pull-Up Resistance pu 39 61 102 kΩ VDDIO = 2.5V 58
Internal Pull-Up Resistance pu 48 99 178 kΩ VDDIO = 1.8V 58
Internal Pull-Down Resistance pd 26 43 79 kΩ VDDIO = 3.3V 58
Internal Pull-Down Resistance pd 34 59 113 kΩ VDDIO = 2.5V 58
Internal Pull-Down Resistance pd 53 99 200 kΩ VDDIO = 1.8V 58
100BASE-TX Peak Differential Output Voltage VO 0.95 1.05 V 100Ω termination across differential output 58
100BASE-TX Output Voltage Imbalance VIMB 2 % 100Ω termination across differential output 58
100BASE-TX Rise/Fall Time tr/tf 3 5 ns 58
100BASE-TX Rise/Fall Time Imbalance 0 0.5 ns 58
100BASE-TX Duty Cycle Distortion -0.25 0.25 ns 58
100BASE-TX Overshoot 5 % 58
10BASE-T Peak Differential Output Voltage VP 2.2 2.8 V 100Ω termination across differential output 59
10BASE-T Jitter Added 3.5 ns Peak-to-peak 59
Supply Voltage VDD_1.2 VIN -0.5 1.8 V 57
Supply Voltage VDDIO, VDDA_3.3 VIN -0.5 5 V 57
Input Voltage (all inputs) -0.5 5 V 57
Output Voltage (all outputs) -0.5 5 V 57
Lead Temperature 260 °C soldering, 10s 57
Storage Temperature TS -55 150 °C 57
Supply Voltage VDDIO_3.3, VDDA_3.3 3.135 3.465 V 57
Supply Voltage VDDIO_2.5 2.375 2.625 V 57
Supply Voltage VDDIO_1.8 1.71 1.89 V 57
Ambient Temperature (Industrial) TA -40 85 °C Industrial 57
Maximum Junction Temperature TJ max. 125 °C 57
Thermal Resistance ΘJA 45.87 °C/W 57
Thermal Resistance ΘJC 15.85 °C/W 57
Supply Current 10BASE-T IDD1_3.3V 41 mA Full-duplex traffic @ 100% utilization 58
Supply Current 100BASE-TX IDD2_3.3V 47 mA Full-duplex traffic @ 100% utilization 58
Supply Current EEE (100 Mbps) Mode IDD3_3.3V 23 mA TX and RX paths in LPI state with no traffic 58
Supply Current EDPD Mode IDD4_3.3V 20 mA Ethernet cable disconnected (Reg. 18h.11 = 0) 58
Supply Current Power-Down Mode IDD5_3.3V 4 mA Software power-down (Reg. 0h.11 = 1) 58
LED Output Drive Current ILED 8 mA Each LED pin (LED0, LED1) 58
100BASE-TX Output Jitter 0.7 ns Peak-to-peak 59
10BASE-T Rise/Fall Time tr/tf 25 ns 59
10BASE-T Squelch Threshold VSQ 400 mV 5 MHz square wave 59
Reference Voltage of ISET VSET 0.65 V R(ISET) = 6.49 kΩ 59
Clock Phase Delay, XI Input to MII TXC Output 15 20 25 ns XI (25 MHz clock input) to MII TXC (25 MHz clock output) delay, referenced to rising edges of both clocks 59
Link Loss Reaction (Indication) Time tllr 4.4 μs Link loss detected at receive differential inputs to PHY signal indication time 59
TXC period (10BASE-T MII SQE) tP 400 ns 60
COL (SQE) delay after TXEN de-asserted tSQE 2.2 μs 60
COL (SQE) pulse duration tSQEP 1 μs 60

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing ppa 1 = RXC clock is stoppable for 100BASE-TX 52

CAD (KiCad official)

  • Symbol: KSZ8091MNXIA-TR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ksz8091mnxia-tr-etched.step / ksz8091mnxia-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8091mnxia-tr.step / ksz8091mnxia-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (80 pp, sha256 a7e3aab56aae2ff4, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF