Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Ray ksz8081rnbia-tr: laser-etched CAD + chip hero (factory 2.0.0 backfill) 1cdec00 19d ago

KSZ8081RNBIA-TR

Microchip Tech · Ethernet Transceivers · QFN-32-EP(5x5)

KSZ8081RNBIA-TR from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground reference. Also tied to the exposed paddle on the bottom of the QFN.
2	VDD_1.2	power_in	1.2V core VDD supplied by the on-chip regulator. Decouple with 2.2 µF and 0.1 µF capacitors to ground.
3	VDDA_3.3	power_in	3.3V analog VDD supply for the PHY analog front end.
4	RXM	bidirectional	Physical receive/transmit signal, negative differential (media-side twisted pair).
5	RXP	bidirectional	Physical receive/transmit signal, positive differential (media-side twisted pair).
6	TXM	bidirectional	Physical transmit/receive signal, negative differential (media-side twisted pair).
7	TXP	bidirectional	Physical transmit/receive signal, positive differential (media-side twisted pair).
8	XO	output	Crystal feedback for the 25 MHz crystal. Leave no-connect if an oscillator or external clock source is used on XI.
9	XI	input	25 MHz mode: 25 MHz ±50 ppm crystal, oscillator or external clock input. 50 MHz mode: 50 MHz ±50 ppm oscillator or external clock input (REF_CLK pin becomes no-connect in this mode).
10	REXT	input	Sets PHY transmit output current. Connect a 6.49 kΩ resistor to ground on this pin.
11	MDIO	bidirectional	Management Interface (MII) data I/O. Weak internal pull-up, open-drain output; requires an external 1.0 kΩ pull-up resistor.
12	MDC	input	Management Interface (MII) clock input, synchronous to MDIO. Internal pull-up.
13	PHYAD0	bidirectional	Strap-in pin: pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of reset. Ipu/O buffer.
14	PHYAD1	bidirectional	Strap-in pin: pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of reset. Ipd/O buffer.
15	RXD1/PHYAD2	bidirectional	RMII Mode: RMII Receive Data Output[1], synchronous to the 50 MHz REF_CLK. Config Mode: latched as PHYADDR[2] at the de-assertion of reset.
16	RXD0/DUPLEX	bidirectional	RMII Mode: RMII Receive Data Output[0], synchronous to the 50 MHz REF_CLK. Config Mode: latched as DUPLEX (pull-up = Half-duplex default, pull-down = Full-duplex) at the de-assertion of reset.
17	VDDIO	power_in	Digital I/O supply: 3.3 V, 2.5 V, or 1.8 V VDD. Sets the digital I/O voltage domain.
18	CRS_DV/CONFIG2	bidirectional	RMII Mode: RMII Carrier Sense/Receive Data Valid output. Config Mode: pull-up/pull-down value is latched as CONFIG2 at the de-assertion of reset (see CONFIG[2:0] mode table).
19	REF_CLK/B-CAST_OFF	bidirectional	RMII Mode: in 25 MHz mode this pin drives the 50 MHz RMII reference clock output to the MAC; in 50 MHz mode this pin is a no-connect (clock enters via XI). Config Mode: pull-up/pull-down value is latched as B-CAST_OFF at the de-assertion of reset.
20	RXER/ISO	bidirectional	RMII Mode: RMII Receive Error output. Config Mode: pull-up/pull-down value is latched as ISOLATE (Pull-up = Enable, Pull-down = Disable default) at the de-assertion of reset.
21	INTRP/NAND_Tree#	bidirectional	Programmable Interrupt Output. Weak internal pull-up, open-drain output; requires an external 1.0 kΩ pull-up resistor. Config Mode: pull-up/pull-down value is latched as NAND_Tree# (Pull-up default = Disable, Pull-down = Enable) at the de-assertion of reset.
22	NC	unconnected	No connect. Pin is not bonded to the die and can be left floating.
23	TXEN	input	RMII Transmit Enable input. When asserted, TXD[1:0] carries valid data from the MAC to the PHY, synchronous to the 50 MHz RMII reference clock.
24	TXD0	input	RMII Transmit Data Input[0], synchronous to the 50 MHz RMII reference clock.
25	TXD1	input	RMII Transmit Data Input[1], synchronous to the 50 MHz RMII reference clock.
26	NC	unconnected	No connect. Pin is not bonded to the die and can be left floating.
27	NC	unconnected	No connect. Pin is not bonded to the die and can be left floating.
28	CONFIG0	bidirectional	Strap-in pin: pull-up/pull-down value is latched as CONFIG0 at the de-assertion of reset. Combined with CONFIG1 and CONFIG2 to select interface mode (001 = RMII, 101 = RMII back-to-back on RNB).
29	CONFIG1	bidirectional	Strap-in pin: pull-up/pull-down value is latched as CONFIG1 at the de-assertion of reset. See CONFIG[2:0] mode encoding.
30	LED0/NWAYEN	bidirectional	Programmable LED0 output; function is selectable via Register 1Fh bits [5:4] (Link/Activity or Link indication). Config Mode: latched as NWAYEN (Pull-up default = enable auto-negotiation, Pull-down = disable) at the de-assertion of reset.
31	LED1/SPEED	bidirectional	Programmable LED1 output; function is selectable via Register 1Fh bits [5:4] (Speed 10/100 or Activity). Config Mode: latched as SPEED (Pull-up default = 100 Mbps, Pull-down = 10 Mbps) at the de-assertion of reset.
32	RST#	input	Active-low chip reset input with internal pull-up.
PAD	GND	power_in	Exposed paddle ground on the bottom of the QFN package. Must be soldered to the PCB ground plane for electrical and thermal return.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-32-EP(5x5)
Category	Interface
Pins	33

Ordering variants

Same part, different packaging or reel option.

KSZ8081RNBIA-TR
KSZ8081MNX

CAD (KiCad official)

Symbol: KSZ8081RNBIA-TR
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: ksz8081rnbia-tr-etched.step / ksz8081rnbia-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8081rnbia-tr.step / ksz8081rnbia-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (66 pp, sha256 773e44836a09f168, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# KSZ8081RNBIA-TR

**Microchip Tech** · Ethernet Transceivers · QFN-32-EP(5x5)

KSZ8081RNBIA-TR from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference. Also tied to the exposed paddle on the bottom of the QFN. |
| 2 | VDD_1.2 | power_in | 1.2V core VDD supplied by the on-chip regulator. Decouple with 2.2 µF and 0.1 µF capacitors to ground. |
| 3 | VDDA_3.3 | power_in | 3.3V analog VDD supply for the PHY analog front end. |
| 4 | RXM | bidirectional | Physical receive/transmit signal, negative differential (media-side twisted pair). |
| 5 | RXP | bidirectional | Physical receive/transmit signal, positive differential (media-side twisted pair). |
| 6 | TXM | bidirectional | Physical transmit/receive signal, negative differential (media-side twisted pair). |
| 7 | TXP | bidirectional | Physical transmit/receive signal, positive differential (media-side twisted pair). |
| 8 | XO | output | Crystal feedback for the 25 MHz crystal. Leave no-connect if an oscillator or external clock source is used on XI. |
| 9 | XI | input | 25 MHz mode: 25 MHz ±50 ppm crystal, oscillator or external clock input. 50 MHz mode: 50 MHz ±50 ppm oscillator or external clock input (REF_CLK pin becomes no-connect in this mode). |
| 10 | REXT | input | Sets PHY transmit output current. Connect a 6.49 kΩ resistor to ground on this pin. |
| 11 | MDIO | bidirectional | Management Interface (MII) data I/O. Weak internal pull-up, open-drain output; requires an external 1.0 kΩ pull-up resistor. |
| 12 | MDC | input | Management Interface (MII) clock input, synchronous to MDIO. Internal pull-up. |
| 13 | PHYAD0 | bidirectional | Strap-in pin: pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of reset. Ipu/O buffer. |
| 14 | PHYAD1 | bidirectional | Strap-in pin: pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of reset. Ipd/O buffer. |
| 15 | RXD1/PHYAD2 | bidirectional | RMII Mode: RMII Receive Data Output[1], synchronous to the 50 MHz REF_CLK. Config Mode: latched as PHYADDR[2] at the de-assertion of reset. |
| 16 | RXD0/DUPLEX | bidirectional | RMII Mode: RMII Receive Data Output[0], synchronous to the 50 MHz REF_CLK. Config Mode: latched as DUPLEX (pull-up = Half-duplex default, pull-down = Full-duplex) at the de-assertion of reset. |
| 17 | VDDIO | power_in | Digital I/O supply: 3.3 V, 2.5 V, or 1.8 V VDD. Sets the digital I/O voltage domain. |
| 18 | CRS_DV/CONFIG2 | bidirectional | RMII Mode: RMII Carrier Sense/Receive Data Valid output. Config Mode: pull-up/pull-down value is latched as CONFIG2 at the de-assertion of reset (see CONFIG[2:0] mode table). |
| 19 | REF_CLK/B-CAST_OFF | bidirectional | RMII Mode: in 25 MHz mode this pin drives the 50 MHz RMII reference clock output to the MAC; in 50 MHz mode this pin is a no-connect (clock enters via XI). Config Mode: pull-up/pull-down value is latched as B-CAST_OFF at the de-assertion of reset. |
| 20 | RXER/ISO | bidirectional | RMII Mode: RMII Receive Error output. Config Mode: pull-up/pull-down value is latched as ISOLATE (Pull-up = Enable, Pull-down = Disable default) at the de-assertion of reset. |
| 21 | INTRP/NAND_Tree# | bidirectional | Programmable Interrupt Output. Weak internal pull-up, open-drain output; requires an external 1.0 kΩ pull-up resistor. Config Mode: pull-up/pull-down value is latched as NAND_Tree# (Pull-up default = Disable, Pull-down = Enable) at the de-assertion of reset. |
| 22 | NC | unconnected | No connect. Pin is not bonded to the die and can be left floating. |
| 23 | TXEN | input | RMII Transmit Enable input. When asserted, TXD[1:0] carries valid data from the MAC to the PHY, synchronous to the 50 MHz RMII reference clock. |
| 24 | TXD0 | input | RMII Transmit Data Input[0], synchronous to the 50 MHz RMII reference clock. |
| 25 | TXD1 | input | RMII Transmit Data Input[1], synchronous to the 50 MHz RMII reference clock. |
| 26 | NC | unconnected | No connect. Pin is not bonded to the die and can be left floating. |
| 27 | NC | unconnected | No connect. Pin is not bonded to the die and can be left floating. |
| 28 | CONFIG0 | bidirectional | Strap-in pin: pull-up/pull-down value is latched as CONFIG0 at the de-assertion of reset. Combined with CONFIG1 and CONFIG2 to select interface mode (001 = RMII, 101 = RMII back-to-back on RNB). |
| 29 | CONFIG1 | bidirectional | Strap-in pin: pull-up/pull-down value is latched as CONFIG1 at the de-assertion of reset. See CONFIG[2:0] mode encoding. |
| 30 | LED0/NWAYEN | bidirectional | Programmable LED0 output; function is selectable via Register 1Fh bits [5:4] (Link/Activity or Link indication). Config Mode: latched as NWAYEN (Pull-up default = enable auto-negotiation, Pull-down = disable) at the de-assertion of reset. |
| 31 | LED1/SPEED | bidirectional | Programmable LED1 output; function is selectable via Register 1Fh bits [5:4] (Speed 10/100 or Activity). Config Mode: latched as SPEED (Pull-up default = 100 Mbps, Pull-down = 10 Mbps) at the de-assertion of reset. |
| 32 | RST# | input | Active-low chip reset input with internal pull-up. |
| PAD | GND | power_in | Exposed paddle ground on the bottom of the QFN package. Must be soldered to the PCB ground plane for electrical and thermal return. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-32-EP(5x5) |
| Category | Interface |
| Pins | 33 |

## Ordering variants

Same part, different packaging or reel option.

- `KSZ8081RNBIA-TR`
- `KSZ8081MNX`

## CAD (KiCad official)

- Symbol: `KSZ8081RNBIA-TR`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `ksz8081rnbia-tr-etched.step` / `ksz8081rnbia-tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ksz8081rnbia-tr.step` / `ksz8081rnbia-tr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881670615273472) (66 pp, sha256 `773e44836a09f168`, retrieved 2026-08-17, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ksz8081rnbia-tr-datasheet.pdf)