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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

KSZ8081RNBCA-TR

Microchip Tech · Ethernet ICs · QFN-32-EP(5x5)

KSZ8081RNBCA-TR from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground.
2	VDD_1.2	power_out	1.2V core VDD supplied by the KSZ8081RNB internal regulator; decouple with 2.2 µF and 0.1 µF capacitors to ground.
3	VDDA_3.3	power_in	3.3V analog VDD; connect to the board 3.3V supply through a ferrite bead and decouple with 22 µF and 0.1 µF to ground.
4	RXM	bidirectional	Physical receive or transmit signal (- differential).
5	RXP	bidirectional	Physical receive or transmit signal (+ differential).
6	TXM	bidirectional	Physical transmit or receive signal (- differential).
7	TXP	bidirectional	Physical transmit or receive signal (+ differential).
8	XO	output	Crystal feedback for the 25 MHz crystal; no connect if an oscillator or external clock source is used.
9	XI	input	25 MHz mode: 25 MHz ±50 ppm crystal/oscillator/external clock input; 50 MHz mode: 50 MHz ±50 ppm oscillator/external clock input.
10	REXT	input	Sets the PHY transmit output current; connect a 6.49 kΩ resistor to ground.
11	MDIO	bidirectional	Management interface data I/O with weak pull-up, open-drain, requiring an external 1.0 kΩ pull-up resistor.
12	MDC	input	Management interface clock input with internal pull-up, synchronous to the MDIO data pin.
13	PHYAD0	bidirectional	Pull-up/pull-down value is latched as PHYADDR[0] at de-assertion of reset (internal pull-up during reset, output otherwise).
14	PHYAD1	bidirectional	Pull-up/pull-down value is latched as PHYADDR[1] at de-assertion of reset (internal pull-down during reset, output otherwise).
15	RXD1/PHYAD2	bidirectional	RMII receive data output [1]; latched as PHYADDR[2] at de-assertion of reset (internal pull-down during reset).
16	RXD0/DUPLEX	bidirectional	RMII receive data output [0]; latched as DUPLEX at de-assertion of reset (internal pull-up during reset).
17	VDDIO	power_in	3.3V, 2.5V, or 1.8V digital VDD; decouple with 22 µF and 0.1 µF to ground.
18	CRS_DV/CONFIG2	bidirectional	RMII carrier sense/receive data valid output; latched as CONFIG2 at de-assertion of reset (internal pull-down during reset).
19	REF_CLK/B-CAST_OFF	bidirectional	In 25 MHz mode outputs the 50 MHz RMII reference clock to the MAC (no connect in 50 MHz mode); latched as B-CAST_OFF at de-assertion of reset.
20	RXER/ISO	bidirectional	RMII receive error output; latched as ISOLATE at de-assertion of reset (internal pull-down during reset).
21	INTRP/NAND_TREE#	bidirectional	Programmable open-drain interrupt output with weak pull-up requiring an external 1.0 kΩ pull-up; latched as NAND Tree# at de-assertion of reset.
22	NC	unconnected	No connect; pin is not bonded and can be left floating.
23	TXEN	input	RMII transmit enable input.
24	TXD0	input	RMII transmit data input [0], synchronous with the 50 MHz RMII reference clock.
25	TXD1	input	RMII transmit data input [1], synchronous with the 50 MHz RMII reference clock; also the NAND tree output.
26	NC	unconnected	No connect; pin is not bonded and can be left floating.
27	NC	unconnected	No connect; pin is not bonded and can be left floating.
28	CONFIG0	bidirectional	Pull-up/pull-down value is latched as CONFIG0 at de-assertion of reset (internal pull-down during reset).
29	CONFIG1	bidirectional	Pull-up/pull-down value is latched as CONFIG1 at de-assertion of reset (internal pull-down during reset).
30	LED0/NWAYEN	bidirectional	Programmable LED0 output (Register 1Fh bits [5:4]); latched as auto-negotiation enable at de-assertion of reset.
31	LED1/SPEED	bidirectional	Programmable LED1 output (Register 1Fh bits [5:4]); latched as speed select (pull-up 100 Mbps, pull-down 10 Mbps) at de-assertion of reset.
32	RST#	input	Chip reset, active low, with internal pull-up.
33	PADDLE	power_in	Exposed paddle on the bottom of the package; ground.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-32-EP(5x5)
Category	Interface ICs
Pins	33

CAD (KiCad official)

Symbol: KSZ8081RNBCA-TR
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: ksz8081rnbca-tr-etched.step / ksz8081rnbca-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8081rnbca-tr.step / ksz8081rnbca-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (66 pp, sha256 773e44836a09f168, retrieved 2026-10-22, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF