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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

KSZ8081MNXCA-TR

Microchip Tech · Ethernet ICs · QFN-32-EP(5x5)

KSZ8081MNXCA-TR from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground connection for the device.
2	VDD_1.2	power_out	1.2V core VDD supplied by the on-chip regulator; decouple with 2.2 µF and 0.1 µF capacitors to ground.
3	VDDA_3.3	power_in	3.3V analog VDD for the transceiver.
4	RXM	bidirectional	Physical receive or transmit signal, differential negative leg.
5	RXP	bidirectional	Physical receive or transmit signal, differential positive leg.
6	TXM	bidirectional	Physical transmit or receive signal, differential negative leg.
7	TXP	bidirectional	Physical transmit or receive signal, differential positive leg.
8	XO	output	Crystal feedback for the 25 MHz crystal; no connect when an oscillator or external clock source is used.
9	XI	input	Crystal, oscillator or external clock input at 25 MHz ±50 ppm.
10	REXT	input	Sets the PHY transmit output current; connect a 6.49 kΩ resistor to ground on this pin.
11	MDIO	bidirectional	MII management data I/O with weak pull-up, open-drain, requiring an external 1.0 kΩ pull-up resistor.
12	MDC	input	MII management clock input, synchronous to the MDIO data pin.
13	RXD3/PHYAD0	bidirectional	MII receive data output bit 3; in config mode the pull-up/pull-down is latched as PHYADDR[0] at reset de-assertion.
14	RXD2/PHYAD1	bidirectional	MII receive data output bit 2; in config mode the pull-up/pull-down is latched as PHYADDR[1] at reset de-assertion.
15	RXD1/PHYAD2	bidirectional	MII receive data output bit 1; in config mode the pull-up/pull-down is latched as PHYADDR[2] at reset de-assertion.
16	RXD0/DUPLEX	bidirectional	MII receive data output bit 0; in config mode the pull-up/pull-down is latched as DUPLEX at reset de-assertion.
17	VDDIO	power_in	3.3V, 2.5V, or 1.8V digital VDD.
18	RXDV/CONFIG2	bidirectional	MII receive data valid output; in config mode the pull-up/pull-down is latched as CONFIG2 at reset de-assertion.
19	RXC/B-CAST_OFF	bidirectional	MII receive clock output; in config mode the pull-up/pull-down is latched as B-CAST_OFF at reset de-assertion.
20	RXER/ISO	bidirectional	MII receive error output; in config mode the pull-up/pull-down is latched as ISOLATE at reset de-assertion.
21	INTRP/NAND_Tree#	bidirectional	Programmable interrupt output with weak pull-up, open-drain, requiring an external 1.0 kΩ pull-up resistor; latched as NAND Tree# at reset de-assertion in config mode.
22	TXC	bidirectional	MII transmit clock output at 2.5 MHz for 10 Mbps or 25 MHz for 100 Mbps; needs a pull-down latched at reset for normal operation.
23	TXEN	input	MII transmit enable input.
24	TXD0	input	MII transmit data input bit 0, synchronous with TXC and valid while TXEN is asserted.
25	TXD1	input	MII transmit data input bit 1, synchronous with TXC and valid while TXEN is asserted.
26	TXD2	input	MII transmit data input bit 2, synchronous with TXC and valid while TXEN is asserted.
27	TXD3	input	MII transmit data input bit 3, synchronous with TXC and valid while TXEN is asserted.
28	COL/CONFIG0	bidirectional	MII collision detect output; in config mode the pull-up/pull-down is latched as CONFIG0 at reset de-assertion.
29	CRS/CONFIG1	bidirectional	MII carrier sense output; in config mode the pull-up/pull-down is latched as CONFIG1 at reset de-assertion.
30	LED0/NWAYEN	bidirectional	Programmable LED0 output; in config mode it is latched as auto-negotiation enable (Register 0h, Bit [12]) at reset de-assertion.
31	LED1/SPEED	bidirectional	Programmable LED1 output; in config mode it is latched as speed select (Register 0h, Bit [13]) at reset de-assertion.
32	RST#	input	Active-low chip reset input with internal pull-up.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-32-EP(5x5)
Category	Interface ICs
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (VDD_1.2)	VIN	-0.5		1.8	V		46
Supply Voltage (VDDIO, VDDA_3.3)	VIN	-0.5		5	V		46
Input Voltage (all inputs)		-0.5		5	V		46
Output Voltage (all outputs)		-0.5		5	V		46
Storage Temperature	TS	-55		150	°C		46
Supply Voltage (VDDIO_3.3, VDDA_3.3)		3.135		3.465	V		46
Supply Voltage (VDDIO_2.5)		2.375		2.625	V		46
Supply Voltage (VDDIO_1.8)		1.71		1.89	V		46
Ambient Temperature (TA, Commercial)	TA	0		70	°C	Commercial	46
Ambient Temperature (TA, Industrial)	TA	-40		85	°C	Industrial	46
Maximum Junction Temperature	TJ			125	°C	TJ max.	46
VIH Input High Voltage	VIH	2			V	VDDIO = 3.3V	47
VIH Input High Voltage	VIH	1.8			V	VDDIO = 2.5V	47
VIH Input High Voltage	VIH	1.3			V	VDDIO = 1.8V	47
VIL Input Low Voltage	VIL			0.8	V	VDDIO = 3.3V	47
VIL Input Low Voltage	VIL			0.7	V	VDDIO = 2.5V	47
VIL Input Low Voltage	VIL			0.5	V	VDDIO = 1.8V	47
Input Current	/IIN/			10	µA	VIN = GND ~ VDDIO	47
VOH Output High Voltage	VOH	2.4			V	VDDIO = 3.3V	47
VOH Output High Voltage	VOH	2			V	VDDIO = 2.5V	47
VOH Output High Voltage	VOH	1.5			V	VDDIO = 1.8V	47
VOL Output Low Voltage	VOL			0.4	V	VDDIO = 3.3V	47
VOL Output Low Voltage	VOL			0.3	V	VDDIO = 1.8V	47
Output Tri-State Leakage	/Ioz/			10	µA		47
Internal Pull-Up Resistance	pu	30	45	73	kΩ	VDDIO = 3.3V	47
Internal Pull-Up Resistance	pu	39	61	102	kΩ	VDDIO = 2.5V	47
Internal Pull-Up Resistance	pu	48	99	178	kΩ	VDDIO = 1.8V	47
Internal Pull-Down Resistance	pd	26	43	79	kΩ	VDDIO = 3.3V	47
Internal Pull-Down Resistance	pd	34	59	113	kΩ	VDDIO = 2.5V	47
Internal Pull-Down Resistance	pd	53	99	200	kΩ	VDDIO = 1.8V	47
Peak Differential Output Voltage (100BASE-TX)	VO	0.95		1.05	V	100Ω termination across differential output	47
Output Voltage Imbalance	VIMB			2	%	100Ω termination across differential output	47
Rise/Fall Time	tr, tf		3	5	ns	100BASE-TX	47
Rise/Fall Time Imbalance			0	0.5	ns		47
Duty Cycle Distortion		-0.25		0.25	ns		47
Overshoot				5	%		47
Peak Differential Output Voltage (10BASE-T)	VP	2.2		2.8	V	100Ω termination across differential output	48
Jitter Added Peak-to-peak				3.5	ns	10BASE-T	48
Rise/Fall Time (10BASE-T)	tr, tf			25	ns	10BASE-T	48
Clock Phase Delay (XI Input to MII TXC Output)		15	20	25	ns	XI (25 MHz) to MII TXC (25 MHz) delay, referenced to rising edges; applies to KSZ8081MNX in MII mode	48

CAD (KiCad official)

Symbol: KSZ8081MNXCA-TR
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: ksz8081mnxca-tr-etched.step / ksz8081mnxca-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8081mnxca-tr.step / ksz8081mnxca-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (66 pp, sha256 773e44836a09f168, retrieved 2026-10-27, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF