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KSZ8041TLI-TR

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Microchip Tech Receivers & Transceivers, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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KSZ8041TLI-TR

Microchip Tech · Receivers & Transceivers · TQFP-48(7x7)

KSZ8041TLI-TR from Microchip Tech, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground.
2 GND power_in Ground.
3 GND power_in Ground.
4 VDDA_1.8 power_in 1.8V analog VDD; connect to V1.8_OUT (pin 6) through a ferrite bead and decouple with 0.1 µF to ground.
5 VDDA_1.8 power_in 1.8V analog VDD; connect to V1.8_OUT (pin 6) through a ferrite bead and decouple with 0.1 µF to ground.
6 V1.8_OUT power_out 1.8V output voltage from the chip's internal regulator; decouple with 1 µF and 0.1 µF capacitors to ground.
7 VDDA_3.3 power_in 3.3V analog VDD; connect to the board's 3.3V supply through a ferrite bead and decouple with 22 µF and 0.1 µF to ground.
8 VDDA_3.3 power_in 3.3V analog VDD; connect to the board's 3.3V supply through a ferrite bead and decouple with 22 µF and 0.1 µF to ground.
9 RX- bidirectional Physical receive or transmit signal (- differential).
10 RX+ bidirectional Physical receive or transmit signal (+ differential).
11 TX- bidirectional Physical transmit or receive signal (- differential).
12 TX+ bidirectional Physical transmit or receive signal (+ differential).
13 GND power_in Ground.
14 XO output Crystal feedback, used only in MII mode with a 25 MHz crystal; no connect if an oscillator or external clock is used, or in RMII or SMII mode.
15 XI/REFCLK/CLOCK input Crystal/oscillator/external clock input: 25 MHz ±50 ppm in MII mode, 50 MHz ±50 ppm in RMII mode (oscillator or external clock only), 125 MHz ±100 ppm in SMII mode (oscillator or external clock only).
16 REXT bidirectional Sets the physical transmit output current; connect a 6.49 kΩ resistor in parallel with a 100 pF capacitor to ground.
17 GND power_in Ground.
18 MDIO bidirectional Management interface (MII) data I/O; requires an external 4.7 kΩ pull-up resistor.
19 MDC input Management interface (MII) clock input, synchronous to the MDIO data interface.
20 RXD3/PHYAD0 bidirectional MII receive data output [3]; internal 40 kΩ ±30% pull-up at power-up/reset, and the level is latched as PHYADDR[0].
21 RXD2/PHYAD1 bidirectional MII receive data output [2]; internal 40 kΩ ±30% pull-down at power-up/reset, and the level is latched as PHYADDR[1].
22 RXD1/RXD[1]/PHYAD2 bidirectional MII/RMII receive data output [1]; internal 40 kΩ ±30% pull-down at power-up/reset, and the level is latched as PHYADDR[2].
23 RXD0/RXD[0]/RX/DUPLEX bidirectional MII/RMII receive data output [0] or SMII receive data and control; internal 40 kΩ ±30% pull-up at power-up/reset, latched as DUPLEX (register 0h bit 8; pull-up = half-duplex default, pull-down = full-duplex).
24 GND power_in Ground.
25 VDDIO_3.3 power_in 3.3V digital VDD; connect to the board's 3.3V supply and decouple with 22 µF and 0.1 µF to ground.
26 VDDIO_3.3 power_in 3.3V digital VDD; connect to the board's 3.3V supply and decouple with 22 µF and 0.1 µF to ground.
27 RXDV/CRSDV/CONFIG2 bidirectional MII receive data valid output or RMII carrier sense/receive data valid output; internal pull-down at power-up/reset, latched as CONFIG2.
28 RXC output MII mode receive clock output.
29 RXER/RX_ER/ISO bidirectional MII/RMII receive error output; internal pull-down at power-up/reset, latched as ISOLATE (pull-up = enable, pull-down default = disable).
30 GND power_in Ground.
31 VDD_1.8 power_in 1.8V digital VDD; connect to V1.8_OUT (pin 6) through a ferrite bead and decouple with 0.1 µF to ground.
32 INTRP output Programmable interrupt output with internal 40 kΩ ±30% pull-up; register 1Bh sets conditions and status, and register 1Fh bit 9 selects active-low (default) or active-high.
33 TXC bidirectional MII mode transmit clock output; transmit clock input in MII back-to-back mode.
34 TXEN/TX_EN input MII/RMII transmit enable input.
35 TXD0/TXD[0]/TX input MII/RMII transmit data input [0], or SMII transmit data and control.
36 TXD1/TXD[1]/SYNC input MII/RMII transmit data input [1], or SMII SYNC clock input.
37 GND power_in Ground.
38 TXD2 input MII mode transmit data input [2].
39 TXD3 input MII mode transmit data input [3].
40 COL/CONFIG0 bidirectional MII collision detect output; internal pull-down at power-up/reset, latched as CONFIG0.
41 CRS/CONFIG1 bidirectional MII carrier sense output; internal pull-down at power-up/reset, latched as CONFIG1.
42 LED0/NWAYEN bidirectional Programmable LED0 output (register 1Eh bits [15:14]; low = link on); internal pull-up at power-up/reset, latched as Auto-Negotiation Enable (register 0h bit 12; pull-up default = enable).
43 LED1/SPEED bidirectional Programmable LED1 output (register 1Eh bits [15:14]); internal pull-up at power-up/reset, latched as SPEED (register 0h bit 13; pull-up default = 100 Mbps, pull-down = 10 Mbps).
44 NC unconnected No connect.
45 NC unconnected No connect.
46 NC unconnected No connect.
47 RST# input Chip reset, active-low.
48 NC unconnected No connect (KSZ8041TL; this pin is FXSD/FXEN only on the KSZ8041FTL).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-48(7x7)
Category Logic ICs
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDD_1.8, VDDA_1.8, V1.8_OUT) -0.5 2.4 V 42
Supply Voltage (VDDIO_3.3, VDDA_3.3) -0.5 4 V 42
Input Voltage (All Inputs) -0.5 4 V 42
Output Voltage (All Outputs) -0.5 4 V 42
Lead Temperature 260 °C soldering, 10s 42
Storage Temperature TS -55 150 °C 42
Supply Voltage (VDDIO_3.3, VDDA_3.3) 3.135 3.465 V Operating ratings 42
Ambient Operating Temperature (Industrial) TA -40 85 °C Industrial 42
Ambient Operating Temperature (Commercial) TA 0 70 °C Commercial 42
Maximum Junction Temperature TJ 125 °C 42
Thermal Resistance Junction-to-Ambient ΘJA 69.64 °C/W 42
Thermal Resistance Junction-to-Case ΘJC 15 °C/W 42
Supply Current 100BASE-TX IDD1 53 58.3 mA Chip only (no transformer); Full-duplex traffic @ 100% utilization 43
Supply Current 10BASE-T IDD2 38 41.8 mA Chip only (no transformer); Full-duplex traffic @ 100% utilization 43
Supply Current Power Saving Mode IDD3 32 35.2 mA Ethernet cable disconnected (reg. 1F.10 = 1) 43
Supply Current Power Down Mode IDD4 4 4.4 mA Software power down (reg. 0.11 = 1) 43
Input High Voltage VIH 2 V 43
Input Low Voltage VIL 0.8 V 43
Input Current IIN -10 10 µA VIN = GND ~ VDDIO 43
Output High Voltage VOH 2.4 V IOH = -4 mA 43
Output Low Voltage VOL 0.4 V IOL = 4 mA 43
Output Tri-State Leakage /IOZ/ 10 µA 43
100BASE-TX Peak Differential Output Voltage VO 0.95 1.05 V 100Ω termination across differential output 43
100BASE-TX Output Voltage Imbalance VIMB 2 % 100Ω termination across differential output 43
100BASE-TX Rise/Fall Time tr/tf 3 5 ns 43
100BASE-TX Rise/Fall Time Imbalance 0 0.5 ns 43
100BASE-TX Duty Cycle Distortion -0.25 0.25 ns 43
100BASE-TX Overshoot 5 % 43
100BASE-TX Output Jitter 0.7 1.4 ns Peak-to-Peak 43
10BASE-T Peak Differential Output Voltage VP 2.2 2.8 V 100Ω termination across differential output 43
10BASE-T Jitter Added 3.5 ns Peak-to-Peak 43
LED Output Drive Current ILED 8 mA Each LED pin (LED0, LED1) 43
Reference Voltage of ISET VSET 0.65 V 43
10BASE-T Rise/Fall Time tr/tf 25 ns 43
10BASE-T Squelch Threshold VSQ 400 mV 5 MHz square wave 43
TXC period tP 400 ns MII SQE timing (10BASE-T) 44
TXC pulse width low tWL 200 ns MII SQE timing (10BASE-T) 44
TXC pulse width high tWH 200 ns MII SQE timing (10BASE-T) 44
COL (SQE) delay after TXEN de-asserted tSQE 2.5 µs MII SQE timing (10BASE-T) 44
COL (SQE) pulse duration tSQEP 1 µs MII SQE timing (10BASE-T) 44

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper If copper mode (FXEN=0), pin strap-in is SPEED mode. 13

CAD (KiCad official)

  • Symbol: KSZ8041TLI-TR
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ksz8041tli-tr-etched.step / ksz8041tli-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8041tli-tr.step / ksz8041tli-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (63 pp, sha256 d048624f52ddf06f, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF