# KSZ8041RNLI-TR

**Microchip Tech** · Pre-ordered Chips · QFN-32(5x5)

KSZ8041RNLI-TR from Microchip Tech, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground connection for the device. |
| 2 | VDDPLL_1.8 | power_out | 1.8V analog VDD from the built-in low-noise regulator, to be decoupled to ground with 1.0 µF and 0.1 µF capacitors. |
| 3 | VDDA_3.3 | power_in | 3.3V analog VDD, to be connected to the board's 3.3V supply through a ferrite bead. |
| 4 | RX- | bidirectional | Physical receive or transmit signal, negative side of the differential pair. |
| 5 | RX+ | bidirectional | Physical receive or transmit signal, positive side of the differential pair. |
| 6 | TX- | bidirectional | Physical transmit or receive signal, negative side of the differential pair. |
| 7 | TX+ | bidirectional | Physical transmit or receive signal, positive side of the differential pair. |
| 8 | XO | output | Crystal feedback for a 25-MHz crystal; left unconnected when an oscillator or external clock source is used. |
| 9 | XI | input | Crystal, oscillator or external clock input at 25 MHz ±50 ppm. |
| 10 | REXT | bidirectional | Sets the physical transmit output current; connect a 6.49-k resistor in parallel with a 100-pF capacitor to ground on this pin. |
| 11 | MDIO | bidirectional | Management interface (MII) data I/O, which requires an external 4.7-k pull-up resistor. |
| 12 | MDC | input | Management interface (MII) clock input, synchronous to the MDIO data interface. |
| 13 | PHYAD0 | bidirectional | Pull-up/pull-down value is latched as PHYADDR[0] during power-up or reset (internal pull-up, 40K ±30%). |
| 14 | PHYAD1 | bidirectional | Pull-up/pull-down value is latched as PHYADDR[1] during power-up or reset (internal pull-down, 40K ±30%). |
| 15 | RXD1/PHYAD2 | bidirectional | RMII receive data output bit 1; pull-up/pull-down value is latched as PHYADDR[2] during power-up or reset. |
| 16 | RXD0/DUPLEX | bidirectional | RMII receive data output bit 0; value is latched as DUPLEX (register 0h, bit 8) during power-up or reset. |
| 17 | VDDIO_3.3 | power_in | 3.3V digital VDD, to be connected to the board's 3.3V supply. |
| 18 | CRSDV/CONFIG2 | bidirectional | RMII carrier sense/receive data valid output; pull-up/pull-down value is latched as CONFIG2 during power-up or reset. |
| 19 | REF_CLK | output | Provides the 50-MHz RMII reference clock output to the MAC. |
| 20 | RXER/RX_ER/ISO | bidirectional | RMII receive error output; pull-up/pull-down value is latched as ISOLATE during power-up or reset. |
| 21 | INTRP | output | Programmable interrupt output, active low by default or active high per register 1Fh bit 9, with internal pull-up (40K ±30%). |
| 22 | NC | unconnected | No connect. |
| 23 | TX_EN | input | RMII transmit enable input, asserted when the MAC presents di-bits on TXD[1:0] for transmission. |
| 24 | TXD0 | input | RMII transmit data input bit 0, accepted for transmission only while TX_EN is asserted. |
| 25 | TXD1 | input | RMII transmit data input bit 1, accepted for transmission only while TX_EN is asserted. |
| 26 | NC | unconnected | No connect. |
| 27 | NC | unconnected | No connect. |
| 28 | CONFIG0 | bidirectional | Pull-up/pull-down value is latched as CONFIG0 during power-up or reset to select the interface mode. |
| 29 | CONFIG1 | bidirectional | Pull-up/pull-down value is latched as CONFIG1 during power-up or reset to select the interface mode. |
| 30 | LED0/NWAYEN | bidirectional | Programmable LED0 output; pull-up/pull-down value is latched as auto-negotiation enable (register 0h, bit 12) during power-up or reset. |
| 31 | LED1/SPEED | bidirectional | Programmable LED1 output; value is latched as SPEED (register 0h, bit 13) during power-up or reset. |
| 32 | RST# | input | Chip reset, active low. |
| 33 | PADDLE GND | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-32(5x5) |
| Category | Interface ICs |
| Pins | 33 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (VDDPLL_1.8) | VDDPLL_1.8 | -0.5 |  | 2.4 | V |  | 38 |
| Supply Voltage (VDDPLL_3.3, VDDPLL_3.3) | VDDPLL_3.3 | -0.5 |  | 4 | V |  | 38 |
| Input Voltage (all inputs) |  | -0.5 |  | 4 | V |  | 38 |
| Output Voltage (all outputs) |  | -0.5 |  | 4 | V |  | 38 |
| Storage Temperature | TS | -55 |  | 150 | °C |  | 38 |
| ESD Performance Rating |  |  |  | 6 | kV | Human body model, 1.5 kΩ in series with 100 pF (Note 5-2) | 38 |
| Supply Voltage (VDDIO_3.3, VDDA_3.3) |  | 3.135 |  | 3.465 | V |  | 38 |
| Ambient Temperature (TA, Industrial) | TA | -40 |  | 85 | °C | Industrial grade | 38 |
| Maximum Junction Temperature (TJ maximum) | TJ |  |  | 125 | °C |  | 38 |
| Input High Voltage | VIH | 2 |  |  | V |  | 39 |
| Input Low Voltage | VIL |  |  | 0.8 | V |  | 39 |
| Input Current | IIN | -10 |  | 10 | µA | VIN = GND ~ VDDIO | 39 |
| Output High Voltage | VOH | 2.4 |  |  | V | IOH = 4 mA | 39 |
| Output Low Voltage | VOL |  |  | 0.4 | V | IOL = 4 mA | 39 |
| Output Tri-State Leakage | /Ioz/ |  |  | 10 | µA |  | 39 |
| Peak Differential Output Voltage (100BASE-TX) | VO | 0.95 |  | 1.05 | V | 100 termination across differential output | 39 |
| Output Voltage Imbalance | VIMB |  |  | 2 | % | 100 termination across differential output | 39 |
| Rise/Fall Time (100BASE-TX) | tr, tf | 3 |  | 5 | ns |  | 39 |
| Rise/Fall Time Imbalance |  | 0 |  | 0.5 | ns |  | 39 |
| Duty Cycle Distortion |  |  |  | 0.25 | ns |  | 39 |
| Overshoot |  |  |  | 5 | % |  | 39 |
| Output Jitter Peak-to-peak |  |  | 0.7 | 1.4 | ns |  | 39 |
| Peak Differential Output Voltage (10BASE-T) | VP | 2.2 |  | 2.8 | V | 100 termination across differential output | 39 |
| Jitter Added Peak-to-peak (10BASE-T) |  |  |  | 3.5 | ns |  | 39 |
| Thermal Resistance (JC) | JC |  | 6 |  | °C/W |  | 38 |

## CAD (KiCad official)

- Symbol: `KSZ8041RNLI-TR`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: QFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files: `ksz8041rnli-tr-etched.step` / `ksz8041rnli-tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ksz8041rnli-tr.step` / `ksz8041rnli-tr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/ksz8041rnli-tr-datasheet.pdf) (58 pp, sha256 `e4c760d80fa0cd50`, retrieved 2026-10-29, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ksz8041rnli-tr-datasheet.pdf)