# KSZ8041RNL-TR

**Microchip Tech** · Buffer/Driver/Transceiver · QFN-32(5x5)

KSZ8041RNL-TR from Microchip Tech, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin for the device. |
| 2 | VDDPLL_1.8 | power_in | 1.8V analog VDD supply, to be decoupled with 1.0 µF and 0.1 µF capacitors to ground. |
| 3 | VDDA_3.3 | power_in | 3.3V analog VDD supply, connected to the board 3.3V supply through a ferrite bead. |
| 4 | RX- | bidirectional | Physical receive or transmit signal, negative differential pin. |
| 5 | RX+ | bidirectional | Physical receive or transmit signal, positive differential pin. |
| 6 | TX- | bidirectional | Physical transmit or receive signal, negative differential pin. |
| 7 | TX+ | bidirectional | Physical transmit or receive signal, positive differential pin. |
| 8 | XO | output | Crystal feedback for a 25-MHz crystal; left unconnected if an oscillator or external clock source is used. |
| 9 | XI | input | Crystal, oscillator or external clock input at 25 MHz ±50 ppm. |
| 10 | REXT | bidirectional | Sets the physical transmit output current; connect a 6.49-k resistor in parallel with a 100-pF capacitor to ground. |
| 11 | MDIO | bidirectional | Management interface (MII) data I/O, which requires an external 4.7-k pull-up resistor. |
| 12 | MDC | input | Management interface (MII) clock input, synchronous to the MDIO data interface. |
| 13 | PHYAD0 | bidirectional | Input with internal pull-up (40K ±30%) latched as PHYADDR[0] at power-up or reset, and an output otherwise. |
| 14 | PHYAD1 | bidirectional | Input with internal pull-down (40K ±30%) latched as PHYADDR[1] at power-up or reset, and an output otherwise. |
| 15 | RXD1 / PHYAD2 | bidirectional | RMII receive data output bit 1, with the pull-up/pull-down value latched as PHYADDR[2] at power-up or reset. |
| 16 | RXD0 / DUPLEX | bidirectional | RMII receive data output bit 0, with the pin value latched as DUPLEX (register 0h bit 8) at power-up or reset. |
| 17 | VDDIO_3.3 | power_in | 3.3V digital VDD supply. |
| 18 | CRSDV/CONFIG2 | bidirectional | RMII carrier sense/receive data valid output, with the pull-up/pull-down value latched as CONFIG2 at power-up or reset. |
| 19 | REF_CLK | output | Provides the 50-MHz RMII reference clock output to the MAC. |
| 20 | RXER/RX_ER/ISO | bidirectional | RMII receive error output, with the pull-up/pull-down value latched as ISOLATE at power-up or reset. |
| 21 | INTRP | output | Programmable interrupt output, active low by default and selectable to active high via register 1Fh bit 9. |
| 22 | NC | unconnected | No connect. |
| 23 | TX_EN | input | RMII transmit enable input from the MAC. |
| 24 | TXD0 | input | RMII transmit data input bit 0 from the MAC, synchronous to REF_CLK. |
| 25 | TXD1 | input | RMII transmit data input bit 1 from the MAC, synchronous to REF_CLK. |
| 26 | NC | unconnected | No connect. |
| 27 | NC | unconnected | No connect. |
| 28 | CONFIG0 | bidirectional | Pull-up/pull-down value latched as CONFIG0 at power-up or reset to select the interface mode. |
| 29 | CONFIG1 | bidirectional | Pull-up/pull-down value latched as CONFIG1 at power-up or reset to select the interface mode. |
| 30 | LED0 / NWAYEN | bidirectional | Programmable LED0 output, with the pin value latched as Auto-Negotiation Enable (register 0h bit 12) at power-up or reset. |
| 31 | LED1 / SPEED | bidirectional | Programmable LED1 output, with the pin value latched as SPEED (register 0h bit 13) at power-up or reset. |
| 32 | RST# | input | Chip reset, active low. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-32(5x5) |
| Category | Logic ICs |
| Pins | 33 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (VDDPLL_1.8) |  | -0.5 |  | 2.4 | V |  | 38 |
| Supply Voltage (VDDPLL_3.3, VDDPLL_3.3) |  | -0.5 |  | 4 | V |  | 38 |
| Input Voltage (all inputs) |  | -0.5 |  | 4 | V |  | 38 |
| Output Voltage (all outputs) |  | -0.5 |  | 4 | V |  | 38 |
| Storage Temperature | TS | -55 |  | 150 | °C |  | 38 |
| ESD Performance Rating |  |  |  | 6 | kV | Human body model, 1.5 kΩ in series with 100 pF | 38 |
| Supply Voltage (VDDIO_3.3, VDDA_3.3) |  | 3.135 |  | 3.465 | V |  | 38 |
| Ambient Temperature (TA, Commercial) | TA | 0 |  | 70 | °C | Commercial | 38 |
| Ambient Temperature (TA, Industrial) | TA | -40 |  | 85 | °C | Industrial | 38 |
| Ambient Temperature (TA, Automotive Qualified) | TA | -40 |  | 85 | °C | Automotive Qualified | 38 |
| Maximum Junction Temperature | TJ |  |  | 125 | °C | TJ maximum | 38 |
| Thermal Resistance (JC) | JC |  | 6 |  | °C/W |  | 38 |
| Input High Voltage | VIH | 2 |  |  | V |  | 39 |
| Input Low Voltage | VIL |  |  | 0.8 | V |  | 39 |
| Input Current | IIN | -10 |  | 10 | µA | VIN = GND ~ VDDIO | 39 |
| Output High Voltage | VOH | 2.4 |  |  | V | IOH = 4 mA | 39 |
| Output Low Voltage | VOL |  |  | 0.4 | V | IOL = 4 mA | 39 |
| Output Tri-State Leakage | /Ioz/ |  |  | 10 | µA |  | 39 |
| Peak Differential Output Voltage (100BASE-TX) | VO | 0.95 |  | 1.05 | V | 100 termination across differential output | 39 |
| Output Voltage Imbalance | VIMB |  |  | 2 | % | 100 termination across differential output | 39 |
| Rise/Fall Time (100BASE-TX) | tr, tf | 3 |  | 5 | ns |  | 39 |
| Rise/Fall Time Imbalance |  | 0 |  | 0.5 | ns |  | 39 |
| Duty Cycle Distortion |  |  |  | 0.25 | ns |  | 39 |
| Overshoot |  |  |  | 5 | % |  | 39 |
| Output Jitter Peak-to-peak |  |  | 0.7 | 1.4 | ns |  | 39 |
| Peak Differential Output Voltage (10BASE-T) | VP | 2.2 |  | 2.8 | V | 100 termination across differential output | 39 |
| Jitter Added Peak-to-peak (10BASE-T) |  |  |  | 3.5 | ns |  | 39 |
| Rise/Fall Time (10BASE-T) | tr, tf |  |  | 25 | ns |  | 39 |

## CAD (KiCad official)

- Symbol: `KSZ8041RNL-TR`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: QFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files: `ksz8041rnl-tr-etched.step` / `ksz8041rnl-tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ksz8041rnl-tr.step` / `ksz8041rnl-tr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/ksz8041rnl-tr-datasheet.pdf) (58 pp, sha256 `e4c760d80fa0cd50`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ksz8041rnl-tr-datasheet.pdf)