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KSZ8041NLI-TR

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Microchip Tech Interface - Specialized, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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KSZ8041NLI-TR

Microchip Tech · Interface - Specialized · QFN-32-EP(5x5)

KSZ8041NLI-TR from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin.
2 VDDPLL_1.8 power_in 1.8V analog VDD supplying the PLL; decouple with 10uF and 0.1uF capacitors to ground.
3 VDDA_3.3 power_in 3.3V analog VDD; connect to the board's 3.3V supply through a ferrite bead.
4 RX- bidirectional Physical receive or transmit signal, negative differential (I/O).
5 RX+ bidirectional Physical receive or transmit signal, positive differential (I/O).
6 TX- bidirectional Physical transmit or receive signal, negative differential (I/O).
7 TX+ bidirectional Physical transmit or receive signal, positive differential (I/O).
8 XO output Crystal feedback, used only in MII mode with a 25 MHz crystal; no connect when an oscillator or external clock is used or in RMII mode.
9 XI / REFCLK input Crystal, oscillator or external clock input: 25MHz +/-50ppm in MII mode, or 50MHz +/-50ppm (oscillator or external clock only) in RMII mode.
10 REXT bidirectional Sets physical transmit output current; pull down with a 6.49KΩ resistor to ground.
11 MDIO bidirectional Management interface (MII) data I/O; requires an external 4.7KΩ pull-up resistor.
12 MDC input Management interface (MII) clock input, synchronous to the MDIO data interface.
13 RXD3 / PHYAD0 bidirectional MII mode receive data output[3]; in config mode the pull-up/pull-down is latched as PHYADDR[0] at power-up/reset.
14 RXD2 / PHYAD1 bidirectional MII mode receive data output[2]; in config mode the pull-up/pull-down is latched as PHYADDR[1] at power-up/reset.
15 RXD1 / RXD[1] / PHYAD2 bidirectional MII mode receive data output[1] or RMII mode receive data output[1]; in config mode the pull-up/pull-down is latched as PHYADDR[2] at power-up/reset.
16 RXD0 / RXD[0] / DUPLEX bidirectional MII mode receive data output[0] or RMII mode receive data output[0]; in config mode latched as DUPLEX at power-up/reset (pull-up = full duplex, pull-down = half duplex).
17 VDDIO_3.3 power_in 3.3V digital VDD; connect to the board's 3.3V supply.
18 RXDV / CRSDV / CONFIG2 bidirectional MII mode receive data valid output or RMII mode carrier sense/receive data valid output; in config mode the pull-up/pull-down is latched as CONFIG2 at power-up/reset.
19 RXC output MII mode receive clock output.
20 RXER / RX_ER / ISO bidirectional MII or RMII receive error output; in config mode the pull-up/pull-down is latched as ISOLATE at power-up/reset (pull-up = enable).
21 INTRP output Programmable interrupt output with internal pull-up; active low by default, active high when register 1Fh bit 9 is set.
22 TXC output MII mode transmit clock output.
23 TXEN / TX_EN input Transmit enable input in MII mode (TXEN) and in RMII mode (TX_EN).
24 TXD0 / TXD[0] input MII mode transmit data input[0] or RMII mode transmit data input[0]; synchronous to TXCLK in MII mode and REF_CLK in RMII mode.
25 TXD1 / TXD[1] input MII mode transmit data input[1] or RMII mode transmit data input[1]; synchronous to TXCLK in MII mode and REF_CLK in RMII mode.
26 TXD2 input MII mode transmit data input[2]; has no effect when TXEN is de-asserted.
27 TXD3 input MII mode transmit data input[3]; has no effect when TXEN is de-asserted.
28 COL / CONFIG0 bidirectional MII mode collision detect output; in config mode the pull-up/pull-down is latched as CONFIG0 at power-up/reset.
29 CRS / CONFIG1 bidirectional MII mode carrier sense output; in config mode the pull-up/pull-down is latched as CONFIG1 at power-up/reset.
30 LED0 / NWAYEN bidirectional Programmable LED0 output (link/activity per register 1Eh bits [15:14], internal pull-up); latched as auto-negotiation enable (register 0h bit 12) at power-up/reset.
31 LED1 / SPEED bidirectional Programmable LED1 output (speed or activity per register 1Eh bits [15:14], internal pull-up); latched as SPEED (pull-up = 100Mbps, pull-down = 10Mbps) at power-up/reset.
32 RST# input Chip reset, active low.
33 PADDLE passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-32-EP(5x5)
Category Interface
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDDPLL_1.8) VDDPLL_1.8 -0.5 2.4 V 31
Supply Voltage (VDDIO_3.3, VDDA_3.3) VDDIO_3.3, VDDA_3.3 -0.5 4 V 31
Input Voltage (all inputs) -0.5 4 V 31
Output Voltage (all outputs) -0.5 4 V 31
Lead Temperature 260 °C soldering, 10sec. 31
Storage Temperature Ts -55 150 °C 31
ESD Rating 6 kV 31
Supply Voltage (VDDIO_3.3, VDDA_3.3) operating VDDIO_3.3, VDDA_3.3 3.135 3.465 V 31
Maximum Junction Temperature TJ Max 125 °C 31
Supply Current 100Base-TX IDD1 53 mA Chip only (no transformer); full-duplex traffic @ 100% utilization 31
Supply Current 10Base-T IDD2 38 mA Chip only (no transformer); full-duplex traffic @ 100% utilization 31
Supply Current Power Saving Mode IDD3 32 mA Ethernet cable disconnected (reg. 1F.10 = 1) 31
Supply Current Power Down Mode IDD4 4 mA Software power down (reg. 0.11 = 1) 31
Input High Voltage (TTL) VIH 2 V 31
Input Low Voltage (TTL) VIL 0.8 V 31
Input Current IIN -10 10 µA VIN = GND ~ VDDIO 31
Output High Voltage (TTL) VOH 2.4 V IOH = -4mA 31
Output Low Voltage (TTL) VOL 0.4 V IOL = 4mA 31
Output Tri-State Leakage /Ioz/ 10 µA 31
Peak Differential Output Voltage (100Base-TX) VO 0.95 1.05 V 100Ω termination across differential output 31
Output Voltage Imbalance (100Base-TX) VIMB 2 % 100Ω termination across differential output 31
Rise/Fall Time (100Base-TX) tr, tf 3 5 ns 31
Rise/Fall Time Imbalance (100Base-TX) 0 0.5 ns 31
Duty Cycle Distortion (100Base-TX) 0.25 ns 31
Overshoot (100Base-TX) 5 % 31
Output Jitter Peak-to-peak (100Base-TX) 0.7 1.4 ns 31
Reference Voltage of ISET VSET 0.65 V 31
Peak Differential Output Voltage (10Base-T) VP 2.2 2.8 V 100Ω termination across differential output 32
Jitter Added (10Base-T) 3.5 ns 32
Rise/Fall Time (10Base-T) tr, tf 25 ns 32
Squelch Threshold (10Base-T) VSQ 400 mV 5MHz square wave 32
TXC period tP 400 ns 33
TXC pulse width low tWL 200 ns 33
TXC pulse width high tWH 200 ns 33
COL (SQE) delay after TXEN de-asserted tSQE 2.5 us 33
COL (SQE) pulse duration tSQEP 1 us 33

CAD (KiCad official)

  • Symbol: KSZ8041NLI-TR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ksz8041nli-tr-etched.step / ksz8041nli-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8041nli-tr.step / ksz8041nli-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (45 pp, sha256 ffd72edb4b1abd53, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF