component

KSZ8041NL-TR

Public Made by Adom

by adom

Microchip Tech Ethernet ICs, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsksz8041nl-trfactory-2.0.0extractor-text

Verified KSZ8041NL-TR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier lcsc, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: KSZ8041NL-TR · QFN-32-EP(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 45-page datasheet
  • ✓distributor: lcsc C11146, digikey 576-1645-2-ND, mouser 998-KSZ8041NLTR
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-s98jmdze/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ksz8041nl-tr.kicad_sym✓ ksz8041nl-tr.kicad_mod✓ ksz8041nl-tr.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers ksz8041nl-tr: viewers · Ray 4d ago
ksz8041nl-tr-etched.glb Publish 0.1.0 · Ray 4d ago
ksz8041nl-tr-etched.step ksz8041nl-tr: factory component page (tier=lcsc) · Ray 4d ago
ksz8041nl-tr-hero.glb ksz8041nl-tr: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
ksz8041nl-tr-hero.overlay.json Publish 0.1.0 · Ray 4d ago
ksz8041nl-tr.glb Publish 0.1.0 · Ray 4d ago
ksz8041nl-tr.kicad_mod Publish 0.1.0 · Ray 4d ago
ksz8041nl-tr.kicad_sym Publish 0.1.0 · Ray 4d ago
ksz8041nl-tr.lbr Publish 0.1.0 · Ray 4d ago
ksz8041nl-tr.step Publish 0.1.0 · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago
verification.json Verified: Published by the parts factory: tier lcsc, 33 pins · Ray 4d ago

KSZ8041NL-TR

Microchip Tech · Ethernet ICs · QFN-32-EP(5x5)

KSZ8041NL-TR from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin.
2 VDDPLL_1.8 power_in 1.8V analog VDD for the PLL, decoupled with 10uF and 0.1uF capacitors to ground.
3 VDDA_3.3 power_in 3.3V analog VDD, connected to the board's 3.3V supply through a ferrite bead.
4 RX- bidirectional Physical receive or transmit signal, negative differential.
5 RX+ bidirectional Physical receive or transmit signal, positive differential.
6 TX- bidirectional Physical transmit or receive signal, negative differential.
7 TX+ bidirectional Physical transmit or receive signal, positive differential.
8 XO output Crystal feedback output, used only in MII mode with a 25 MHz crystal and left unconnected for an oscillator, external clock, or RMII mode.
9 XI / REFCLK input Crystal, oscillator, or external clock input: 25MHz +/-50ppm in MII mode, or 50MHz +/-50ppm (oscillator or external clock only) in RMII mode.
10 REXT bidirectional Sets the physical transmit output current; pull down to ground with a 6.49KΩ resistor.
11 MDIO bidirectional Management Interface (MII) data I/O, requiring an external 4.7KΩ pull-up resistor.
12 MDC input Management Interface (MII) clock input, synchronous to the MDIO data interface.
13 RXD3 / PHYAD0 bidirectional MII mode receive data output bit 3, and the pull-up/pull-down value is latched as PHYADDR[0] at power-up/reset.
14 RXD2 / PHYAD1 bidirectional MII mode receive data output bit 2, and the pull-up/pull-down value is latched as PHYADDR[1] at power-up/reset.
15 RXD1 / RXD[1] / PHYAD2 bidirectional MII mode receive data output bit 1 or RMII mode receive data output bit 1, and the pull-up/pull-down value is latched as PHYADDR[2] at power-up/reset.
16 RXD0 / RXD[0] / DUPLEX bidirectional MII mode receive data output bit 0 or RMII mode receive data output bit 0, and the strap is latched as DUPLEX (register 0h bit 8) at power-up/reset, with pull-up defaulting to full duplex.
17 VDDIO_3.3 power_in 3.3V digital VDD, connected to the board's 3.3V supply.
18 RXDV / CRSDV / CONFIG2 bidirectional Receive data valid output in MII mode or carrier sense/receive data valid output in RMII mode, with the CONFIG2 strap latched at power-up/reset.
19 RXC output MII mode receive clock output.
20 RXER / RX_ER / ISO bidirectional Receive error output in MII or RMII mode, with the ISO strap latched into register 0h bit 10 at power-up/reset (pull-up enables isolate).
21 INTRP output Programmable interrupt output with internal pull-up, active low by default and selectable active high via register 1Fh bit 9.
22 TXC output MII mode transmit clock output.
23 TXEN / TX_EN input Transmit enable input in MII mode (TXEN) or RMII mode (TX_EN).
24 TXD0 / TXD[0] input MII mode transmit data input bit 0 or RMII mode transmit data input bit 0.
25 TXD1 / TXD[1] input MII mode transmit data input bit 1 or RMII mode transmit data input bit 1.
26 TXD2 input MII mode transmit data input bit 2, synchronous to TXCLK.
27 TXD3 input MII mode transmit data input bit 3, synchronous to TXCLK.
28 COL / CONFIG0 bidirectional MII mode collision detect output, with the CONFIG0 strap latched at power-up/reset.
29 CRS / CONFIG1 bidirectional MII mode carrier sense output, with the CONFIG1 strap latched at power-up/reset.
30 LED0 / NWAYEN bidirectional Programmable LED0 output (register 1Eh bits [15:14]), with the strap latched as auto-negotiation enable (register 0h bit 12) at power-up/reset.
31 LED1 / SPEED bidirectional Programmable LED1 output (register 1Eh bits [15:14]), with the strap latched as speed select (register 0h bit 13) at power-up/reset, where pull-up selects 100Mbps.
32 RST# input Chip reset input, active low.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-32-EP(5x5)
Category Interface ICs
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDDIO_3.3, VDDA_3.3) VDDIO_3.3, VDDA_3.3 3.135 3.465 V 31
Ambient Temperature TA 0 70 °C 31
Supply Voltage (VDDPLL_1.8) VDDPLL_1.8 -0.5 2.4 V 31
Supply Voltage (VDDIO_3.3, VDDA_3.3) VDDIO_3.3, VDDA_3.3 -0.5 4 V 31
Input Voltage (all inputs) -0.5 4 V 31
Output Voltage (all outputs) -0.5 4 V 31
Lead Temperature 260 °C soldering, 10 sec. 31
Storage Temperature Ts -55 150 °C 31
ESD Rating 6 kV Human body model, 1.5k in series with 100pF 31
Maximum Junction Temperature TJ Max 125 °C 31
100Base-TX Supply Current IDD1 53 mA Chip only (no transformer); Full-duplex traffic @ 100% utilization 31
10Base-T Supply Current IDD2 38 mA Chip only (no transformer); Full-duplex traffic @ 100% utilization 31
Power Saving Mode Supply Current IDD3 32 mA Ethernet cable disconnected (reg. 1F.10 = 1) 31
Power Down Mode Supply Current IDD4 4 mA Software power down (reg. 0.11 = 1) 31
Input High Voltage (TTL) VIH 2 V 31
Input Low Voltage (TTL) VIL 0.8 V 31
Input Current IIN -10 10 µA VIN = GND ~ VDDIO 31
Output High Voltage (TTL) VOH 2.4 V IOH = -4mA 31
Output Low Voltage (TTL) VOL 0.4 V IOL = 4mA 31
Output Tri-State Leakage /Ioz/ 10 µA 31
Peak Differential Output Voltage (100Base-TX) VO 0.95 1.05 V 100Ω termination across differential output 31
Output Voltage Imbalance (100Base-TX) VIMB 2 % 100Ω termination across differential output 31
Rise/Fall Time (100Base-TX) tr, tf 3 5 ns 31
Rise/Fall Time Imbalance (100Base-TX) 0 0.5 ns 31
Duty Cycle Distortion (100Base-TX) -0.25 0.25 ns 31
Overshoot (100Base-TX) 5 % 31
Output Jitter Peak-to-peak (100Base-TX) 0.7 1.4 ns 31
Peak Differential Output Voltage (10Base-T) VP 2.2 2.8 V 100Ω termination across differential output 32
Jitter Added Peak-to-peak (10Base-T) 3.5 ns 32
Rise/Fall Time (10Base-T) tr, tf 25 ns 32
Reference Voltage of ISET VSET 0.65 V 31
Squelch Threshold VSQ 400 mV 5MHz square wave 32
TXC Period tP 400 ns 33
TXC Pulse Width Low tWL 200 ns 33
TXC Pulse Width High tWH 200 ns 33
COL (SQE) Delay after TXEN De-asserted tSQE 2.5 µs 33
COL (SQE) Pulse Duration tSQEP 1 µs 33

CAD (KiCad official)

  • Symbol: KSZ8041NL-TR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ksz8041nl-tr-etched.step / ksz8041nl-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8041nl-tr.step / ksz8041nl-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (45 pp, sha256 ffd72edb4b1abd53, retrieved 2026-11-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF