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KP201CSGA

KIWI · AC-DC Controllers & Regulators · SOP-8

KP201CSGA from KIWI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CT output Overload protection time setting pin; an external capacitor to ground sets the overload protection time.
2 VDD power_in Chip supply pin; recommended 10 to 28 V operating range, 33 V absolute maximum, with UVLO on at 21 V typ and off at 9 V typ.
3 FB input Feedback input connected to the optocoupler in closed loop; its voltage sets the PWM drive frequency and the CS turn-off threshold (-0.3 to 7 V).
4 CS input Current sense input and CS OVP detection pin (-0.3 to 7 V), with CS OVP threshold of 250 mV.
5 NTC passive External OTP detection pin, with 110 uA detection current and 1.0 V trigger threshold.
6 NC unconnected No connection.
7 GND power_in Chip ground.
8 GATE output Totem-pole gate drive output connected to the external MOSFET, with 13 V output high clamp and 20 V absolute maximum.

Key specifications

Parameter Value
Manufacturer KIWI
Package SOP-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD DC supply voltage VDD 33 V 4
VDD DC clamp current 10 mA 4
FB, CS, NTC, CT voltage -0.3 7 V 4
GATE voltage 20 V 4
Package thermal resistance (SOP-8) 150 oC/W SOP-8 4
Maximum junction temperature TJ 150 oC 4
Storage temperature range -65 150 oC 4
Soldering temperature 260 oC soldering, 10 s 4
ESD human body model 3 kV 4
VDD supply voltage VDD 10 28 V 4
Operating ambient temperature TA -40 85 oC 4
VDD startup current IVDD_st 2 20 uA TA=25C, VDD=18V 4
VDD operating current IVDD_Op 1.2 2 mA VFB=3V, GATE=1nF 4
VDD quiescent current IVDD_standby 0.6 1 mA 4
VDD turn-on voltage VDD_ON 19 21 21.5 V 4
VDD turn-off voltage VDD_OFF 8 9 10 V 4
VDD OVP threshold VDD_OVP 29 31 33 V 4
VDD clamp voltage VDD_Clamp 33 35 37 V I(VDD) = 7 mA 4
Normal operating frequency FOSC 60 65 70 KHz 5
Frequency shuffling range ΔFshuffle/FOSC -4 4 % 5
Maximum duty cycle DMAX 70 75 80 % 5
Turbo maximum operating frequency center FTurbo_OSC 125 130 135 KHz Duty>=60% 5

CAD (KiCad official)

  • Symbol: KP201CSGA
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: kp201csga-etched.step / kp201csga-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); kp201csga.step / kp201csga.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: KIWI datasheet (8 pp, sha256 621f91c11c02eb91, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF