KiCad - the KiCad Bridge
Public Made by Adomby adom
Drive your own KiCad from an AI, in the background: open every editor, read the whole board as data (the EDA Bridge Standard board model), stack-up, part heights, netlists, place, route, pour, DRC and exports.
kicad_placement_validate: outline box ignores a large arc's bulge; nested annular courtyards reported as overlapping
KiCad Bridge 1.0.58, KiCad 10.0.3 (arav-rog, Windows), caller Linux via adom-aiflow 0.2.17 place verify. Observed 2026-10-24 on a round capacitive-encoder sensor (146 mm ring with a 44 x 20 mm tab, a 45 mm bore).
1. The outline box misses a large arc's bulge. The board's outer edge was one Edge.Cuts arc of about 340 degrees (start and end at the tab, mid at the top). kicad_placement_validate reported outline: {minX 78.0, maxX 122.5, minY 26.9, maxY 193.1}: the arc's three points, the tab's lines and the bore circle, but not the arc's sideways extent (the true box is x 26.9 to 173.1). Every footprint near the ring then came back in outsideOutline (10 of 34, among them mounting holes 2 mm inside the edge). Drawing the same edge as 34 arcs of 10 degrees made outsideOutline empty. Expected: bound an arc by its true extent (include the 0/90/180/270 degree points it sweeps), or flatten it finely.
2. Nested ring courtyards reported as overlapping. Concentric electrode and guard footprints each drew their courtyard as two F.CrtYd circles (an annulus: e.g. E2 23.0/31.95 mm, G2 43.8/47.7, E4 48.0/56.95, G3 57.25/59.25, all centred on one point). The rings do not overlap, and native DRC reports no courtyards_overlap, but courtyardOverlaps listed E2 against E4, G2 and G3 (only E2, and not against G1/E1/E3), so placed: false. Redrawing each courtyard as one closed C-shaped fp_poly (outer arc, a 0.1 mm slit, inner arc back) gave placed: true, overlaps empty. Expected: read a footprint's courtyard as KiCad does (nested outlines as holes, even-odd) and test the polygons, like native DRC; related to the bounding-box report on kicad_move_footprint courtyards.
Workarounds are in the board generator (10-degree edge arcs, C-shaped ring courtyards); no bridge source or install was changed. Evidence: the run's placement-verify.json before and after on ut-austin-ece-364d/uta-bldc-dyno-showroom (actuator-cell/output-board/aiflow-run).