KiCad - the KiCad Bridge - Commit

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1.0.61: Every Konnect v0.13.0 capability, 211 verbs (was 133; docs/konnect-gap.md maps all 228 Konnect tools). Schematic: components, pins, items, rotate, region move, annotate, replace and update symbols, field reset, wire delete/split, labels, junctions, net stubs, pin-to-pin wiring, text, buses, atomic batches, sheets and hierarchy, sheet pins, connectivity trace, checks, connectivity fixes, PNG render with visual baselines, design review. Board: outline, layer count, graphics, mounting holes, SVG import, refill, save, add/flip/delete/edit/align footprints, update footprints from library, footprint graphics and 3D models, selection and cross-probe, update PCB from schematic. Routing and rules: modify track, diff pairs, copy routing, netclasses, board rules, custom rules, clearance check, placement score, decoupling placement, fanout plan. Fab: DXF, GenCAD, IPC-2581, ODB++, IPC-D-356, one-zip fab package, fab pre-flight, cost numbers. Projects and libraries: create, info, rename, snapshot; footprint and symbol create, edit, info; library search. PCM: file:// and private wiki repositories, zipPath installs (#132).

John Lauer ·39ff8a63a9 ·14d ago ·parent baad156

6 files changed +12841

rust/crates/kicad-core/tests/fixtures/sch_hier/mcu-kicad10.svg+8612 rust/crates/kicad-core/tests/fixtures/sch_hier/mcu.kicad_sch+1608 rust/crates/kicad-core/tests/fixtures/sch_hier/power.kicad_sch+1391 rust/crates/kicad-core/tests/konnect_route.rs+409 rust/crates/kicad-core/tests/sch_edit.rs+477 rust/crates/kicad-core/tests/sch_hier.rs+344

rust/crates/kicad-core/tests/fixtures/sch_hier/mcu-kicad10.svgadded+8612

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rust/crates/kicad-core/tests/fixtures/sch_hier/mcu.kicad_schadded+1608

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default)+					)+					(fill+						(type none)+					)+				)+				(polyline+					(pts+						(xy -2.032 -0.762) (xy 2.032 -0.762)+					)+					(stroke+						(width 0.508)+						(type default)+					)+					(fill+						(type none)+					)+				)+			)+			(symbol "C_1_1"+				(pin passive line+					(at 0 3.81 270)+					(length 2.794)+					(name ""+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+					(number "1"+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+				)+				(pin passive line+					(at 0 -3.81 90)+					(length 2.794)+					(name ""+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+					(number "2"+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+				)+			)+			(embedded_fonts no)+		)+		(symbol "power:GND"+			(power global)+			(pin_numbers+				(hide yes)+			)+			(pin_names+				(offset 0)+				(hide yes)+			)+			(exclude_from_sim no)+			(in_bom yes)+			(on_board yes)+			(in_pos_files yes)+			(duplicate_pin_numbers_are_jumpers no)+			(property "Reference" "#PWR"+				(at 0 -6.35 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "Value" "GND"+				(at 0 -3.81 0)+				(show_name no)+				(do_not_autoplace no)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "Footprint" ""+				(at 0 0 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "Datasheet" ""+				(at 0 0 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "Description" "Power symbol creates a global label with name \"GND\" , ground"+				(at 0 0 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "ki_keywords" "global power"+				(at 0 0 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yes)+			)+		)+		(property "Description" "Generic connector, single row, 01x01, script generated"+			(at 111.76 60.96 0)+			(effects+				(font+					(size 1.27 1.27)+				)+				(hide yes)+			)+		)+		(pin "1"+			(uuid "df138a0b-7eda-4d58-b7e2-5d9d2e85e5c6")+		)+		(instances+			(project "hier"+				(path "/4b27afbc-6492-4606-90bb-981fbb98399d/441f215d-5859-45bf-b43f-cf9fdb3aed52"+					(reference "J3")+					(unit 1)+				)+			)+		)+	)+	(wire+		(pts+			(xy 124.46 73.66) (xy 124.46 60.96)+		)+		(stroke+			(width 0)+			(type default)+		)+		(uuid "46490eef-cfb4-4290-9cee-56f2e57b3689")+	)+	(wire+		(pts+			(xy 124.46 60.96) (xy 116.84 60.96)+		)+		(stroke+			(width 0)+			(type default)+		)+		(uuid "c3a952a4-02b1-4386-a207-77827c3ebca2")+	)+	(label "VIO"+		(at 120.65 60.96 0)+		(effects+			(font+				(size 1.27 1.27)+			)+			(justify left bottom)+		)+		(uuid "479c4b4f-c6d2-4ba0-8df4-afacfdd4c3ff")+	)+	(wire+		(pts+			(xy 124.46 104.14) (xy 124.46 106.68)+		)+		(stroke+			(width 0)+			(type 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"Datasheet" ""+			(at 124.46 106.68 0)+			(effects+				(font+					(size 1.27 1.27)+				)+				(hide yes)+			)+		)+		(property "Description" "Power symbol creates a global label with name \"GND\" , ground"+			(at 124.46 106.68 0)+			(effects+				(font+					(size 1.27 1.27)+				)+				(hide yes)+			)+		)+		(pin "1"+			(uuid "ec1b0f9b-139c-4a73-96de-36d34d9a2ba8")+		)+		(instances+			(project "hier"+				(path "/4b27afbc-6492-4606-90bb-981fbb98399d/441f215d-5859-45bf-b43f-cf9fdb3aed52"+					(reference "#PWR11")+					(unit 1)+				)+			)+		)+	)+	(wire+		(pts+			(xy 142.24 91.44) (xy 162.56 91.44)+		)+		(stroke+			(width 0)+			(type default)+		)+		(uuid "0a25d29f-a559-4076-b108-48d42d3377e6")+	)+	(hierarchical_label "SDA"+		(shape bidirectional)+		(at 162.56 91.44 0)+		(fields_autoplaced yes)+		(effects+			(font+				(size 1.27 1.27)+			)+			(justify left)+		)+		(uuid "1a800159-d108-4f66-bcc2-e73ec6720300")+	)+	(symbol+		(lib_id "Device:R")+		(at 157.48 95.25 0)+		(unit 1)+		(exclude_from_sim no)+		(in_bom yes)+		(on_board yes)+		(dnp no)+		(fields_autoplaced yes)+		(uuid "a24e0cf0-5ae2-4b93-b1db-c07895e2a3be")+		(property "Reference" "R1"+			(at 160.02 93.98 0)+			(effects+				(font+					(size 1.27 1.27)+				)+				(justify left)+			)+		)+		(property "Value" "4k7"+			(at 160.02 96.52 0)+			(effects+				(font+					(size 1.27 1.27)+				)+				(justify left)+			)+		)+		(property "Footprint" ""+			(at 157.48 95.25 0)+			(effects+				(font+					(size 1.27 1.27)+				)+				(hide yes)+			)+		)+		(property "Datasheet" ""+			(at 157.48 95.25 0)+			(effects+				(font+					(size 1.27 1.27)+				)+				(hide yes)+			)+		)+		(property "Description" "Resistor"+			(at 157.48 95.25 0)+			(effects+				(font+					(size 1.27 1.27)+				)+				(hide yes)+			)+		)+		(pin "1"+			(uuid "10d99eec-a5d7-468c-a60e-832ca4502d84")+		)+		(pin "2"+			(uuid "412bb018-8986-4480-a8fc-fe78309a5773")+		)+		(instances+			(project "hier"+				(path "/4b27afbc-6492-4606-90bb-981fbb98399d/441f215d-5859-45bf-b43f-cf9fdb3aed52"+					(reference "R1")+					(unit 1)+				)+			)+		)+	)+	(junction+		(at 157.48 91.44)+		(diameter 0)+		(color 0 0 0 0)+		(uuid "6003bcec-e9ba-4746-a7f3-0ef4c50ba50d")+	)+	(symbol+		(lib_id "power:+3V3")+		(at 157.48 99.06 180)+		(unit 1)+		(exclude_from_sim no)+		(in_bom yes)+		(on_board yes)+		(dnp no)+		(fields_autoplaced yes)+		(uuid "29752cc9-e079-4d87-a0b6-9e7650a37588")+		(property "Reference" "#PWR12"+			(at 160.02 97.79 0)+			(effects+				(font+					(size 1.27 1.27)+				)+				(justify left)+				(hide yes)+			)+		)+		(property "Value" "+3V3"+			(at 160.02 100.33 0)+			(effects+				(font+					(size 1.27 1.27)+				)+				(justify left)+			)+		)+		(property "Footprint" ""+			(at 157.48 99.06 0)+			(effects+				(font+					(size 1.27 1.27)+				)+				(hide yes)+			)+		)+		(property "Datasheet" ""+			(at 157.48 99.06 0)+			(effects+				(font+					(size 1.27 1.27)+				)+				(hide yes)+			)+		)+		(property "Description" "Power symbol creates a global label with name \"+3V3\""+			(at 157.48 99.06 0)+			(effects+				(font+					(size 1.27 1.27)+				)+				(hide yes)+			)+		)+		(pin "1"+			(uuid "cd1b768c-8b92-4bb5-aa6d-b8e4d9f27bd6")+		)+		(instances+			(project "hier"+				(path "/4b27afbc-6492-4606-90bb-981fbb98399d/441f215d-5859-45bf-b43f-cf9fdb3aed52"+					(reference "#PWR12")+					(unit 1)+				)+			)+		)+	)+	(wire+		(pts+			(xy 142.24 86.36) (xy 162.56 86.36)+		)+		(stroke+			(width 0)+			(type default)+		)+		(uuid "28d44c75-8a78-4a8d-9262-1828dcdfcc09")+	)+	(hierarchical_label "SCL"+		(shape input)+		(at 162.56 86.36 0)+		(fields_autoplaced yes)+		(effects+			(font+				(size 1.27 1.27)+			)+			(justify left)+		)+		(uuid "3970910a-7f40-44a5-a4de-4564397c4da9")+	)+	(sheet_instances+		(path "/"+			(page "1")+		)+	)+	(embedded_fonts no)+)

rust/crates/kicad-core/tests/fixtures/sch_hier/power.kicad_schadded+1391

@@ -0,0 +1,1391 @@+(kicad_sch+	(version 20260306)+	(generator "eeschema")+	(generator_version "10.0")+	(uuid "70e67ea7-bb87-45d2-970c-334311ef7ef5")+	(paper "A4")+	(title_block+		(title "Power")+		(date "2026-10-27")+		(rev "A")+	)+	(lib_symbols+		(symbol "Regulator_Linear:AP2112K-3.3"+			(pin_names+				(offset 0.254)+			)+			(exclude_from_sim no)+			(in_bom yes)+			(on_board yes)+			(in_pos_files yes)+			(duplicate_pin_numbers_are_jumpers no)+			(property "Reference" "U"+				(at -5.08 5.715 0)+				(show_name no)+				(do_not_autoplace no)+				(effects+					(font+						(size 1.27 1.27)+					)+					(justify left)+				)+			)+			(property "Value" "AP2112K-3.3"+				(at 0 5.715 0)+				(show_name no)+				(do_not_autoplace no)+				(effects+					(font+						(size 1.27 1.27)+					)+					(justify left)+				)+			)+			(property "Footprint" "Package_TO_SOT_SMD:SOT-23-5"+				(at 0 8.255 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "Datasheet" "https://www.diodes.com/assets/Datasheets/AP2112.pdf"+				(at 0 2.54 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "Description" "600mA low dropout linear regulator, with enable pin, 3.8V-6V input voltage range, 3.3V fixed positive output, SOT-23-5"+				(at 0 0 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "ki_keywords" "linear regulator ldo fixed positive"+				(at 0 0 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "ki_fp_filters" "SOT?23?5*"+				(at 0 0 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(symbol "AP2112K-3.3_0_1"+				(rectangle+					(start -5.08 4.445)+					(end 5.08 -5.08)+					(stroke+						(width 0.254)+						(type default)+					)+					(fill+						(type background)+					)+				)+			)+			(symbol "AP2112K-3.3_1_1"+				(pin power_in line+					(at -7.62 2.54 0)+					(length 2.54)+					(name "VIN"+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+					(number "1"+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+				)+				(pin power_in line+					(at 0 -7.62 90)+					(length 2.54)+					(name "GND"+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+					(number "2"+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+				)+				(pin input line+					(at -7.62 0 0)+					(length 2.54)+					(name "EN"+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+					(number "3"+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+				)+				(pin no_connect line+					(at 5.08 0 180)+					(length 2.54)+					(hide yes)+					(name "NC"+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+					(number "4"+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+				)+				(pin power_out line+					(at 7.62 2.54 180)+					(length 2.54)+					(name "VOUT"+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+					(number "5"+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+				)+			)+			(embedded_fonts no)+		)+		(symbol "power:+5V"+			(power global)+			(pin_numbers+				(hide yes)+			)+			(pin_names+				(offset 0)+				(hide yes)+			)+			(exclude_from_sim no)+			(in_bom yes)+			(on_board yes)+			(in_pos_files yes)+			(duplicate_pin_numbers_are_jumpers no)+			(property "Reference" "#PWR"+				(at 0 -3.81 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "Value" "+5V"+				(at 0 3.556 0)+				(show_name no)+				(do_not_autoplace no)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "Footprint" ""+				(at 0 0 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "Datasheet" ""+				(at 0 0 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "Description" "Power symbol creates a global label with name \"+5V\""+				(at 0 0 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "ki_keywords" "global power"+				(at 0 0 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(symbol "+5V_0_1"+				(polyline+					(pts+						(xy -0.762 1.27) (xy 0 2.54)+					)+					(stroke+						(width 0)+						(type default)+					)+					(fill+						(type none)+					)+				)+				(polyline+					(pts+						(xy 0 2.54) (xy 0.762 1.27)+					)+					(stroke+						(width 0)+						(type default)+					)+					(fill+						(type none)+					)+				)+				(polyline+					(pts+						(xy 0 0) (xy 0 2.54)+					)+					(stroke+						(width 0)+						(type default)+					)+					(fill+						(type none)+					)+				)+			)+			(symbol "+5V_1_1"+				(pin power_in line+					(at 0 0 90)+					(length 0)+					(name ""+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+					(number "1"+						(effects+							(font+								(size 1.27 1.27)+							)+						)+					)+				)+			)+			(embedded_fonts no)+		)+		(symbol "Device:C"+			(pin_numbers+				(hide yes)+			)+			(pin_names+				(offset 0.254)+			)+			(exclude_from_sim no)+			(in_bom yes)+			(on_board yes)+			(in_pos_files yes)+			(duplicate_pin_numbers_are_jumpers no)+			(property "Reference" "C"+				(at 0.635 2.54 0)+				(show_name no)+				(do_not_autoplace no)+				(effects+					(font+						(size 1.27 1.27)+					)+					(justify left)+				)+			)+			(property "Value" "C"+				(at 0.635 -2.54 0)+				(show_name no)+				(do_not_autoplace no)+				(effects+					(font+						(size 1.27 1.27)+					)+					(justify left)+				)+			)+			(property "Footprint" ""+				(at 0.9652 -3.81 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "Datasheet" ""+				(at 0 0 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "Description" "Unpolarized capacitor"+				(at 0 0 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property "ki_keywords" "cap capacitor"+				(at 0 0 0)+				(show_name no)+				(do_not_autoplace no)+				(hide yes)+				(effects+					(font+						(size 1.27 1.27)+					)+				)+			)+			(property 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rust/crates/kicad-core/tests/konnect_route.rsadded+409

@@ -0,0 +1,409 @@+//! The konnect-route fixture project (tests/fixtures/konnect-route: a KiCad 10 board, its+//! .kicad_pro, .kicad_dru, a kicadxml netlist and a project footprint library) through the+//! routing, rules, placement-helper and update-from-schematic planners.++use std::path::{Path, PathBuf};++use serde_json::{json, Value};++use kicad_core::libraries::LibCtx;+use kicad_core::{netlist, pcb, pcb_sync, place_tools, placement, project_rules, route_tools};++fn dir() -> PathBuf {+    Path::new(env!("CARGO_MANIFEST_DIR")).join("tests/fixtures/konnect-route")+}++fn board() -> (String, pcb::Board) {+    let p = dir().join("route-fixture.kicad_pcb");+    let text = std::fs::read_to_string(&p).unwrap();+    let b = pcb::parse_pcb_text(&text, &p.to_string_lossy()).unwrap();+    (text, b)+}++fn project() -> Value {+    project_rules::read_json(&dir().join("route-fixture.kicad_pro")).unwrap()+}++fn net_names(b: &pcb::Board) -> Vec<String> {+    b.nets.iter().map(|n| n.name.clone()).collect()+}++/// A scratch copy of the whole fixture folder.+fn scratch(tag: &str) -> PathBuf {+    let d = std::env::temp_dir().join(format!("kb-konnect-route-{tag}-{}", std::process::id()));+    let _ = std::fs::remove_dir_all(&d);+    copy_dir(&dir(), &d);+    d+}++fn copy_dir(from: &Path, to: &Path) {+    std::fs::create_dir_all(to).unwrap();+    for e in std::fs::read_dir(from).unwrap() {+        let e = e.unwrap();+        let t = to.join(e.file_name());+        if e.file_type().unwrap().is_dir() {+            copy_dir(&e.path(), &t);+        } else {+            std::fs::copy(e.path(), t).unwrap();+        }+    }+}++const SIG_A_1: &str = "00000000-0000-4000-8000-000000000074";++#[test]+fn the_fixture_is_a_kicad_10_board() {+    let (_, b) = board();+    assert_eq!(b.net_format, pcb::NetFormat::Name);+    assert_eq!(b.footprints.len(), 7);+    assert_eq!(b.segments.len(), 3);+    assert_eq!(b.vias.len(), 1);+    let o = placement::outline(&b).unwrap();+    assert_eq!((o.min_x, o.min_y, o.max_x, o.max_y), (0.0, 0.0, 60.0, 40.0));+    let u1 = b.footprints.iter().find(|f| f.reference == "U1").unwrap();+    assert_eq!(u1.pads.iter().find(|p| p.number == "5").unwrap().rotation, Some(90.0), "pad angles are read");+}++// ---------------------------------------------------------------------------+// kicad_netclasses, kicad_board_rules, kicad_custom_rules+// ---------------------------------------------------------------------------++#[test]+fn netclasses_report_patterns_and_the_nets_they_match() {+    let (_, b) = board();+    let r = project_rules::netclasses_report(&project(), &net_names(&b));+    let usb = r["classes"].as_array().unwrap().iter().find(|c| c["name"] == "USB").unwrap();+    assert_eq!(usb["diffPairGap"], 0.15);+    assert_eq!(usb["patterns"][0]["pattern"], "USB_*");+    assert_eq!(usb["nets"], json!(["USB_D+", "USB_D-"]));+    let default = r["classes"].as_array().unwrap().iter().find(|c| c["name"] == "Default").unwrap();+    assert!(default["nets"].as_array().unwrap().contains(&json!("GND")));+    assert_eq!(project_rules::class_for_net(&project(), "USB_D-")["name"], "USB");+}++#[test]+fn netclass_edits_create_assign_and_remove_and_write_atomically() {+    let d = scratch("netclass");+    let pro_path = d.join("route-fixture.kicad_pro");+    let before = std::fs::read_to_string(&pro_path).unwrap();+    let mut pro: Value = serde_json::from_str(&before).unwrap();+    let changes = project_rules::edit_netclasses(&mut pro, &json!({"set": {"name": "PWR", "trackWidth": 0.5, "clearance": 0.3}, "assign": {"netclass": "PWR", "patterns": ["+3V3"]}})).unwrap();+    assert_eq!(changes.len(), 2, "{changes:?}");+    let pwr = project_rules::class_for_net(&pro, "+3V3");+    assert_eq!(pwr["name"], "PWR");+    assert_eq!(pwr["track_width"], 0.5);+    assert_eq!(pwr["via_diameter"], 0.6, "a new class starts from the Default values");+    assert!(project_rules::edit_netclasses(&mut pro, &json!({"set": {"name": "PWR", "trackWidth": 0.5}})).unwrap().is_empty(), "no change, no change list");+    assert_eq!(project_rules::edit_netclasses(&mut pro, &json!({"assign": {"netclass": "NOPE", "patterns": ["x"]}})).unwrap_err().code, "unknown_netclass");+    assert_eq!(project_rules::edit_netclasses(&mut pro, &json!({"set": {"name": "BAD", "viaDiameter": 0.3, "viaDrill": 0.4}})).unwrap_err().code, "invalid_value");+    let bak = project_rules::write_atomic(&pro_path, &project_rules::project_text(&pro), Some(&before)).unwrap();+    assert_eq!(std::fs::read_to_string(&bak).unwrap(), before);+    let back = project_rules::read_json(&pro_path).unwrap();+    assert_eq!(project_rules::class_for_net(&back, "+3V3")["name"], "PWR");+    assert_eq!(project_rules::write_atomic(&pro_path, "{}", Some(&before)).unwrap_err().code, "file_changed");+    let mut p2 = back.clone();+    project_rules::edit_netclasses(&mut p2, &json!({"remove": "PWR"})).unwrap();+    assert_eq!(project_rules::class_for_net(&p2, "+3V3")["name"], "Default");+    assert!(p2["net_settings"]["netclass_patterns"].as_array().unwrap().iter().all(|p| p["netclass"] != "PWR"));+    assert!(project_rules::open_locks(&pro_path).is_empty());+    std::fs::write(d.join("~route-fixture.kicad_pcb.lck"), "x").unwrap();+    assert_eq!(project_rules::open_locks(&pro_path).len(), 1);+    let _ = std::fs::remove_dir_all(&d);+}++#[test]+fn board_rules_read_and_write_with_the_hidden_zero_rows() {+    let mut pro = project();+    let r = project_rules::board_rules_report(&pro);+    assert_eq!(r["constraints"]["minClearance"], 0.15);+    assert_eq!(r["constraints"]["minCopperEdgeClearance"], 0.5);+    assert_eq!(r["trackWidths"], json!([0.2, 0.3, 0.5]));+    assert_eq!(r["viaSizes"], json!([{"diameter": 0.6, "drill": 0.3}]));+    let ch = project_rules::edit_board_rules(&mut pro, &json!({"rules": {"minTrackWidth": 0.127, "min_hole_to_hole": 0.3}, "trackWidths": [0.15, 0.25], "viaSizes": [{"diameter": 0.45, "drill": 0.2}], "diffPairs": [{"width": 0.2, "gap": 0.15}]})).unwrap();+    assert_eq!(ch.len(), 5, "{ch:?}");+    assert_eq!(pro["board"]["design_settings"]["track_widths"], json!([0.0, 0.15, 0.25]));+    assert_eq!(pro["board"]["design_settings"]["via_dimensions"][0], json!({"diameter": 0.0, "drill": 0.0}));+    assert_eq!(pro["board"]["design_settings"]["rules"]["min_track_width"], 0.127);+    let r = project_rules::board_rules_report(&pro);+    assert_eq!(r["diffPairs"], json!([{"width": 0.2, "gap": 0.15, "viaGap": 0.15}]));+    assert_eq!(project_rules::edit_board_rules(&mut pro, &json!({"rules": {"minWiggle": 1}})).unwrap_err().code, "unknown_rule");+    assert_eq!(project_rules::edit_board_rules(&mut pro, &json!({"viaSizes": [{"diameter": 0.3, "drill": 0.3}]})).unwrap_err().code, "invalid_value");+}++#[test]+fn the_fixture_rules_file_parses_and_edits() {+    let text = std::fs::read_to_string(dir().join("route-fixture.kicad_dru")).unwrap();+    let (v, rules) = project_rules::parse_dru(&text).unwrap();+    assert_eq!(v, Some(1));+    assert_eq!(rules.iter().map(|r| r.name.as_str()).collect::<Vec<_>>(), vec!["HV clearance", "Inner thin"]);+    assert_eq!(rules[1].layer.as_deref(), Some("inner"));+    assert_eq!(rules[1].constraints[0]["opt"], "0.15mm");+    let rule = project_rules::rule_text(&json!({"name": "USB pair", "condition": "A.NetClass == 'USB'", "constraints": [{"type": "diff_pair_gap", "min": 0.15, "max": 0.2}, {"type": "skew", "max": 0.1}]})).unwrap();+    let added = project_rules::add_rule(&text, &rule, false).unwrap();+    assert_eq!(project_rules::parse_dru(&added).unwrap().1.len(), 3);+    let (gone, removed) = project_rules::remove_rules(&added, &["HV clearance".into()]).unwrap();+    assert_eq!(removed.len(), 1);+    assert!(gone.contains("Inner thin") && gone.contains("USB pair") && !gone.contains("HV clearance"));+}++// ---------------------------------------------------------------------------+// kicad_modify_track, kicad_route_diff_pair, kicad_copy_routing+// ---------------------------------------------------------------------------++#[test]+fn a_track_change_rewrites_only_that_segment() {+    let (text, b) = board();+    let (changes, cand) = route_tools::plan_track_changes(&b, &text, &json!({"changes": [{"id": SIG_A_1, "width": 0.3, "layer": "B.Cu"}]})).unwrap();+    assert_eq!(changes[0].changed, vec!["width", "layer"]);+    assert_eq!(changes[0].net, "SIG_A");+    let nb = pcb::parse_pcb_text(&cand, "c").unwrap();+    assert_eq!(nb.segments.len(), 3);+    let s = nb.segments.iter().find(|s| s.uuid.as_deref() == Some(SIG_A_1)).unwrap();+    assert_eq!((s.width, s.layer.as_deref(), s.net_name.as_deref()), (Some(0.3), Some("B.Cu"), Some("SIG_A")));+    let others_before: Vec<_> = b.segments.iter().filter(|s| s.uuid.as_deref() != Some(SIG_A_1)).map(|s| (s.uuid.clone(), s.width, s.layer.clone())).collect();+    let others_after: Vec<_> = nb.segments.iter().filter(|s| s.uuid.as_deref() != Some(SIG_A_1)).map(|s| (s.uuid.clone(), s.width, s.layer.clone())).collect();+    assert_eq!(others_before, others_after);+    // an endpoint onto a pad+    let (c2, cand2) = route_tools::plan_track_changes(&b, &text, &json!({"id": SIG_A_1, "end": [12, 19.675]})).unwrap();+    assert_eq!(c2[0].after.end, [12.0, 19.675]);+    assert!(cand2.contains("(end 12 19.675)"));+    let e = |a: Value| route_tools::plan_track_changes(&b, &text, &a).unwrap_err().code;+    assert_eq!(e(json!({"id": "nope", "width": 0.3})), "unknown_track");+    assert_eq!(e(json!({"id": "00000000-0000-4000-8000-000000000076", "width": 0.3})), "unknown_track", "a via is not a track");+    assert_eq!(e(json!({"id": SIG_A_1, "layer": "In7.Cu"})), "unknown_layer");+    assert_eq!(e(json!({"id": SIG_A_1, "width": 0.2})), "no_change");+}++#[test]+fn a_diff_pair_takes_the_netclass_gap_and_reports_skew() {+    let (text, b) = board();+    let pro = project();+    let plan = route_tools::plan_diff_pair(&b, Some(&pro), &json!({"pair": "USB_D", "centerline": [[15, 36], [25, 36], [27, 38]]})).unwrap();+    let v = plan.public();+    assert_eq!((v["netP"].as_str(), v["netN"].as_str()), (Some("USB_D+"), Some("USB_D-")));+    assert_eq!((v["width"].as_f64(), v["gap"].as_f64()), (Some(0.2), Some(0.15)), "the USB netclass values");+    assert_eq!(v["sizesFrom"], "netclass");+    // centre-to-centre spacing is gap + width on the straight run+    let p0 = plan.p.segments[0].start;+    let n0 = plan.n.segments[0].start;+    assert!(((p0[1] - n0[1]).abs() - 0.35).abs() < 1e-6, "{p0:?} {n0:?}");+    assert!(p0[1] < n0[1], "P is on the left of +x travel (smaller y)");+    // on the outside of a right turn the left half is longer+    assert!(v["skewMm"].as_f64().unwrap() > 0.0);+    let cand = pcb::splice(&text, &plan.blocks());+    assert_eq!(pcb::parse_pcb_text(&cand, "c").unwrap().segments.len(), 3 + 4);+    // a layer change puts a via pair at the vias' spacing+    let plan = route_tools::plan_diff_pair(&b, Some(&pro), &json!({"netP": "USB_D+", "centerline": [[15, 36], [25, 36], {"x": 30, "y": 36, "layer": "B.Cu"}, [35, 36]], "viaSize": 0.6})).unwrap();+    assert_eq!((plan.p.vias.len(), plan.n.vias.len()), (1, 1));+    let (vp, vn) = (plan.p.vias[0].at, plan.n.vias[0].at);+    assert!(((vp[1] - vn[1]).abs() - (0.6 + 0.25)).abs() < 1e-6, "via pair centre spacing is viaSize + viaGap: {vp:?} {vn:?}");+    assert_eq!(plan.p.segments.last().unwrap().layer, "B.Cu");+    // pads join the ends, and pcb::plan checks they are on the right nets+    let ok = route_tools::plan_diff_pair(&b, None, &json!({"netP": "USB_D+", "netN": "USB_D-", "centerline": [[20, 24], [26, 24]], "pEnd": "J1.2", "nEnd": "J1.3", "gap": 0.2, "width": 0.25})).unwrap();+    assert_eq!(ok.public()["sizesFrom"], "arguments");+    assert_eq!(ok.p.segments.last().unwrap().end, [30.0, 28.54]);+    let wrong = route_tools::plan_diff_pair(&b, None, &json!({"netP": "USB_D+", "netN": "USB_D-", "centerline": [[20, 24], [26, 24]], "pEnd": "J1.3"})).unwrap_err();+    assert_eq!(wrong.code, "net_mismatch");+    assert_eq!(route_tools::plan_diff_pair(&b, None, &json!({"pair": "NOPE", "centerline": [[0, 0], [1, 0]]})).unwrap_err().code, "pair_not_found");+}++#[test]+fn copy_routing_translates_and_remaps_nets() {+    let (text, b) = board();+    let src = json!({"minX": 9, "minY": 19, "maxX": 19, "maxY": 29});+    let plan = route_tools::plan_copy(&b, &json!({"source": src, "offset": {"dx": 30, "dy": -15}})).unwrap();+    let v = plan.public();+    assert_eq!((v["segmentCount"].as_u64(), v["viaCount"].as_u64()), (Some(2), Some(1)), "the B.Cu run leaves the box and stays");+    assert_eq!(plan.plans[0].net_name, "SIG_A");+    assert_eq!(plan.plans[0].vias[0].at, [40.0, 13.0]);+    let cand = pcb::splice(&text, &plan.blocks());+    assert_eq!(pcb::parse_pcb_text(&cand, "c").unwrap().vias.len(), 2);+    let remap = route_tools::plan_copy(&b, &json!({"source": src, "offset": [30, -15], "netMap": {"SIG_A": "SIG_B"}})).unwrap();+    assert_eq!(remap.plans.iter().map(|p| p.net_name.as_str()).collect::<Vec<_>>(), vec!["SIG_B"]);+    // a footprint pair that maps no net leaves nothing to copy, and says why+    let none = route_tools::plan_copy(&b, &json!({"source": src, "offset": [30, -15], "refMap": {"U1": "U2"}})).unwrap_err();+    assert_eq!(none.code, "nothing_to_copy");+    assert_eq!(none.detail["skipped"][0]["reason"], "unmapped_net");+    assert_eq!(route_tools::plan_copy(&b, &json!({"source": src, "offset": [0, 0]})).unwrap_err().code, "invalid_geometry");+}++// ---------------------------------------------------------------------------+// kicad_check_clearance, kicad_score_placement, kicad_place_decoupling, kicad_plan_fanout+// ---------------------------------------------------------------------------++#[test]+fn clearance_by_courtyard_and_by_pad() {+    let (_, b) = board();+    let c = place_tools::check_clearance(&b, &json!({"threshold": 3})).unwrap();+    let pairs = c["pairs"].as_array().unwrap();+    let c1c2 = pairs.iter().find(|p| p["a"] == "C1" && p["b"] == "C2").expect("C1-C2 under 3 mm");+    assert!((c1c2["distanceMm"].as_f64().unwrap() - 2.14).abs() < 1e-6);+    assert!(place_tools::check_clearance(&b, &json!({})).unwrap()["clean"] == true, "nothing under 0.25 mm");+    let only = place_tools::check_clearance(&b, &json!({"threshold": 50, "refs": ["R1"]})).unwrap();+    assert!(only["pairs"].as_array().unwrap().iter().all(|p| p["a"] == "R1" || p["b"] == "R1"));+    let pads = place_tools::check_clearance(&b, &json!({"mode": "pads", "threshold": 3.5})).unwrap();+    let p = pads["pairs"].as_array().unwrap().iter().find(|p| p["a"] == "C1.2" && p["b"] == "C2.1").expect("C1.2 to C2.1");+    assert!((p["distanceMm"].as_f64().unwrap() - (4.0 - 0.96 - 0.56)).abs() < 1e-6, "{p}");+    assert_eq!(place_tools::check_clearance(&b, &json!({"refs": ["Q9"]})).unwrap_err().code, "unknown_footprint");+}++#[test]+fn the_score_names_its_deductions() {+    let (_, b) = board();+    let s = place_tools::score(&b, &json!({}));+    let rule = |name: &str| s["deductions"].as_array().unwrap().iter().find(|d| d["rule"] == name).cloned().unwrap();+    assert_eq!(rule("connector_off_edge")["items"][0]["ref"], "J1");+    assert_eq!(rule("decoupling_far")["count"], 2);+    assert_eq!(rule("courtyard_overlap")["count"], 0);+    assert_eq!(rule("outside_board")["count"], 0);+    let sc = s["score"].as_f64().unwrap();+    assert!(sc < 90.0 && sc > 50.0, "{s}");+}++#[test]+fn decoupling_caps_go_beside_the_power_pins() {+    let (_, b) = board();+    let plan = place_tools::plan_decoupling(&b, &json!({"ic": "U1"})).unwrap();+    assert_eq!(plan["validation"]["ok"], true, "{plan}");+    let rows = plan["placements"].as_array().unwrap();+    assert_eq!(rows.len(), 2);+    let c1 = rows.iter().find(|r| r["ref"] == "C1").unwrap();+    let c2 = rows.iter().find(|r| r["ref"] == "C2").unwrap();+    assert_eq!((c1["pin"].as_str(), c1["side"].as_str()), (Some("U1.1"), Some("left")));+    assert_eq!((c2["pin"].as_str(), c2["side"].as_str()), (Some("U1.5"), Some("bottom")));+    assert!(c1["padToPinMm"].as_f64().unwrap() < 2.0 && c2["padToPinMm"].as_f64().unwrap() < 2.0, "{plan}");+    // the power pad faces the IC: C1 at 180 puts pad 1 (+3V3) on its right, toward U1+    assert_eq!(c1["rotation"], 180.0);+    // moveArgs is a kicad_move_footprint batch the move planner accepts+    let mv = placement::plan_moves(&b, &plan["moveArgs"]).unwrap();+    assert_eq!(mv.moves.len(), 2);+    let after = place_tools::score(&b, &json!({}));+    let moved = {+        let mut t = std::fs::read_to_string(dir().join("route-fixture.kicad_pcb")).unwrap();+        for m in &mv.moves {+            t = t.replace(&format!("(at {} {})", pcb::num(m.before.x), pcb::num(m.before.y)), &format!("(at {} {} {})", pcb::num(m.after.x), pcb::num(m.after.y), pcb::num(m.after.rotation)));+        }+        pcb::parse_pcb_text(&t, "m").unwrap()+    };+    let better = place_tools::score(&moved, &json!({}));+    assert!(better["score"].as_f64() > after["score"].as_f64(), "placing the caps raises the score: {} -> {}", after["score"], better["score"]);+    assert_eq!(place_tools::plan_decoupling(&b, &json!({"ic": "R1"})).unwrap_err().code, "no_caps");+}++fn route_net_accepts(b: &pcb::Board, calls: &[Value]) {+    for c in calls {+        pcb::plan(b, c).unwrap_or_else(|e| panic!("kicad_route_net would refuse {c}: {} {}", e.code, e.message));+    }+}++#[test]+fn a_bga_fanout_plan_is_route_net_ready() {+    let (_, b) = board();+    let f = place_tools::plan_fanout(&b, &json!({"ref": "U2"})).unwrap();+    assert_eq!(f["package"], "bga");+    assert_eq!(f["pitchMm"], 0.8);+    assert_eq!(f["style"], "dogbone");+    assert_eq!(f["escapeLayer"], "B.Cu", "a two-layer board escapes to the back");+    let rows = f["pads"].as_array().unwrap();+    assert_eq!(rows.iter().filter(|r| r["style"] == "surface").count(), 12, "the outer ring escapes on top");+    assert_eq!(rows.iter().filter(|r| r["style"] == "dogbone").count(), 4);+    let b2 = rows.iter().find(|r| r["pad"] == "U2.B2").unwrap();+    assert_eq!(b2["via"]["at"], json!([41.2, 19.2]), "away from the centre, on the diagonal");+    assert!(f["minViaToPadMm"].as_f64().unwrap() >= 0.1, "{f}");+    route_net_accepts(&b, f["calls"].as_array().unwrap());+    let vip = place_tools::plan_fanout(&b, &json!({"ref": "U2", "style": "via-in-pad"})).unwrap();+    route_net_accepts(&b, vip["calls"].as_array().unwrap());+    let tight = place_tools::plan_fanout(&b, &json!({"ref": "U2", "viaSize": 0.6, "viaDrill": 0.3})).unwrap();+    assert_eq!(tight["style"], "via-in-pad", "a 0.6 mm via does not fit between 0.8 mm balls");+}++#[test]+fn a_qfn_fanout_plan_stubs_out_and_stitches_the_exposed_pad() {+    let (_, b) = board();+    let f = place_tools::plan_fanout(&b, &json!({"ref": "U1"})).unwrap();+    assert_eq!(f["package"], "perimeter");+    assert_eq!(f["pitchMm"], 0.65);+    let rows = f["pads"].as_array().unwrap();+    let ep = rows.iter().find(|r| r["pad"] == "U1.17").unwrap();+    assert_eq!(ep["style"], "thermal-via-grid");+    assert_eq!(ep["vias"].as_array().unwrap().len(), 9, "a 3 x 3 grid at 1 mm in the 2.6 mm pad");+    let p3 = rows.iter().find(|r| r["pad"] == "U1.3").unwrap();+    assert_eq!(p3["edge"], "left");+    assert!(p3["stubEnd"][0].as_f64().unwrap() < 18.05 - 0.4);+    let p6 = rows.iter().find(|r| r["pad"] == "U1.6").unwrap();+    assert_eq!(p6["style"], "skip", "a pad with no net is not fanned out");+    route_net_accepts(&b, f["calls"].as_array().unwrap());+    assert_eq!(place_tools::plan_fanout(&b, &json!({"ref": "C1"})).unwrap_err().code, "not_a_package");+}++// ---------------------------------------------------------------------------+// kicad_update_pcb_from_schematic+// ---------------------------------------------------------------------------++fn fixture_netlist() -> netlist::Netlist {+    netlist::parse_kicadxml(&std::fs::read_to_string(dir().join("route-fixture.net")).unwrap()).unwrap()+}++#[test]+fn the_netlist_carries_symbol_uuids() {+    let nl = fixture_netlist();+    let r2 = nl.component("R2").unwrap();+    assert_eq!(pcb_sync::symbol_path(r2).as_deref(), Some("/10000000-0000-4000-8000-000000000007"));+}++#[test]+fn the_plan_lists_every_difference() {+    let (text, b) = board();+    let d = pcb_sync::compare(&b, &text, &fixture_netlist());+    assert_eq!(d["missingFootprints"], json!([{"ref": "R2", "value": "4k7", "footprint": "Fixture:R_0603_1608Metric"}]));+    assert_eq!(d["extraFootprints"][0]["ref"], "MH1");+    assert_eq!(d["changedValues"], json!([{"ref": "C2", "from": "100n", "to": "1u"}]));+    assert_eq!(d["changedFootprints"][0]["ref"], "J1");+    assert_eq!(d["padNetChanges"], json!([{"pad": "R1.2", "from": "SIG_B", "to": "SIG_C"}]));+    assert_eq!(d["relinks"], json!([]));+    assert_eq!(d["inSync"], false);+}++#[test]+fn apply_on_the_closed_file_brings_the_board_in_sync() {+    let d = scratch("sync");+    let path = d.join("route-fixture.kicad_pcb");+    let text = std::fs::read_to_string(&path).unwrap();+    let b = pcb::parse_pcb_text(&text, &path.to_string_lossy()).unwrap();+    let nl = fixture_netlist();+    let ctx = LibCtx::default();+    let module = |id: &str| pcb_sync::resolve_footprint(id, &d, &ctx).and_then(|p| std::fs::read_to_string(p).map_err(|e| e.to_string()));+    let (out, done) = pcb_sync::apply(&text, &b, &nl, &pcb_sync::ApplyOpts { delete_extra: false, update_footprints: true }, &module).unwrap();+    assert_eq!(done["footprintsAdded"][0]["ref"], "R2", "{done}");+    assert_eq!(done["footprintsReplaced"][0]["to"], "Fixture:PinHeader_1x04_P2.00mm_Vertical");+    assert_eq!(done["valuesUpdated"][0]["ref"], "C2");+    assert_eq!(done["extrasMarked"], json!(["MH1"]));+    assert_eq!(done["notApplied"], json!([]));+    pcb::write_board(&path, &out, true, Some(&text)).unwrap();+    let after = pcb::parse_pcb(&path).unwrap();+    let again = pcb_sync::compare(&after, &out, &nl);+    assert_eq!(again["changeCount"], 1, "only the marked extra is left: {again}");+    assert_eq!(again["extraFootprints"][0]["ref"], "MH1");+    let r2 = after.footprints.iter().find(|f| f.reference == "R2").unwrap();+    assert_eq!(r2.value, "4k7");+    assert_eq!(r2.path.as_deref(), Some("/10000000-0000-4000-8000-000000000007"));+    let pos = r2.position.as_ref().unwrap();+    assert!(pos.y > 40.0, "new parts land in a row below the board: {pos:?}");+    assert_eq!(r2.pads.iter().map(|p| p.net_name.clone().unwrap_or_default()).collect::<Vec<_>>(), vec!["+3V3", "SIG_B"]);+    let j1 = after.footprints.iter().find(|f| f.reference == "J1").unwrap();+    assert_eq!(j1.position.as_ref().map(|p| (p.x, p.y)), Some((30.0, 26.0)), "a replaced footprint keeps its place");+    assert_eq!(j1.pads[2].net_name.as_deref(), Some("USB_D-"));+    assert!(out.contains(pcb_sync::EXTRA_MARK));+    // ids stay unique+    let ids: Vec<&str> = out.match_indices("(uuid \"").map(|(i, _)| &out[i + 7..i + 43]).collect();+    let mut sorted = ids.clone();+    sorted.sort();+    sorted.dedup();+    assert_eq!(sorted.len(), ids.len(), "duplicate uuids");+    // deleteExtra removes it+    let (out2, done2) = pcb_sync::apply(&out, &after, &nl, &pcb_sync::ApplyOpts { delete_extra: true, update_footprints: true }, &module).unwrap();+    assert_eq!(done2["extrasDeleted"], json!(["MH1"]));+    let after2 = pcb::parse_pcb_text(&out2, "x").unwrap();+    assert_eq!(pcb_sync::compare(&after2, &out2, &nl)["inSync"], true);+    let _ = std::fs::remove_dir_all(&d);+}

rust/crates/kicad-core/tests/sch_edit.rsadded+477

@@ -0,0 +1,477 @@+//! The newer schematic edits (`kicad_core::sch_edit`) on a KiCad 10 fixture+//! (`fixtures/sch-edit/edit10.kicad_sch`, version 20260306, built from the KiCad 10 stock+//! Device, Amplifier_Operational and power libraries and loaded by KiCad 10.0.2's ERC):+//! pin geometry for rotated and multi-unit parts, the junction rule, wire delete and split,+//! multi-unit move with wire stretch, rotate, region move, annotate across sheets, symbol+//! replace and library refresh, field reset, labels, text, buses. Every edited text must+//! parse again. When `service-kicad` is on PATH, KiCad 10 itself checks an edited sheet.++use std::collections::BTreeSet;+use std::path::{Path, PathBuf};+use std::process::Command;++use kicad_core::sch_edit::*;+use kicad_core::schematic::*;++fn fixture_dir() -> PathBuf {+    Path::new(env!("CARGO_MANIFEST_DIR")).join("tests/fixtures/sch-edit")+}++fn fixture() -> String {+    std::fs::read_to_string(fixture_dir().join("edit10.kicad_sch")).expect("edit10.kicad_sch readable")+}++fn sch() -> Schematic {+    Schematic::parse(&fixture()).unwrap()+}++fn minilib(name: &str) -> Node {+    load_lib_symbol(&fixture_dir().join("MiniLib.kicad_sym"), name).unwrap().block+}++fn reparse(s: &Schematic) -> Schematic {+    let text = s.to_text();+    let again = Schematic::parse(&text).expect("edited text parses again");+    assert_eq!(again.to_text(), text, "and writes back byte identical");+    again+}++fn pin(s: &Schematic, spec: &str) -> PinInfo {+    s.find_pin(spec).unwrap_or_else(|e| panic!("{spec}: {e}"))+}++fn temp_dir(tag: &str) -> PathBuf {+    let d = std::env::temp_dir().join(format!("kicad-core-schedit-{tag}-{}-{}", std::process::id(), new_uuid()));+    std::fs::create_dir_all(&d).unwrap();+    d+}++#[test]+fn fixture_is_kicad_10_and_round_trips() {+    let text = fixture();+    let s = Schematic::parse(&text).unwrap();+    assert_eq!(s.version().as_deref(), Some("20260306"));+    assert_eq!(s.to_text(), text);+}++#[test]+fn components_list_units_and_fields() {+    let s = sch();+    let all = s.components(None);+    let refs: Vec<String> = all.iter().map(|c| c["reference"].as_str().unwrap().to_string()).collect();+    // R? twice (two separate parts), U? once (two units of one unannotated part would still be+    // two entries: each X? instance is its own part until annotated)+    assert_eq!(refs.iter().filter(|r| *r == "R?").count(), 2);+    let u1 = all.iter().find(|c| c["reference"] == "U1").unwrap();+    assert_eq!(u1["libId"], "Amplifier_Operational:LM358");+    assert_eq!(u1["unitCount"], 3);+    let units: Vec<u64> = u1["units"].as_array().unwrap().iter().map(|u| u["unit"].as_u64().unwrap()).collect();+    assert_eq!(units, vec![1, 2, 3]);+    assert!(u1["fields"].as_array().unwrap().iter().any(|f| f["name"] == "Value" && f["value"] == "LM358"));+    let only = s.components(Some(&["R2".to_string()]));+    assert_eq!(only.len(), 1);+    assert_eq!(only[0]["units"][0]["rotation"], 90.0);+}++#[test]+fn pins_follow_rotation_and_units() {+    let s = sch();+    let r1 = s.pins_of("R1").unwrap();+    assert_eq!(r1.iter().map(|p| (p.number.as_str(), p.at)).collect::<Vec<_>>(), vec![("1", (100.33, 46.99)), ("2", (100.33, 54.61))]);+    assert_eq!(dir_name(r1[0].out), "up");+    assert_eq!(dir_name(r1[1].out), "down");+    // R2 is turned 90: pin 1 on the left, where KiCad's ERC accepts the no-connect flag+    let p = pin(&s, "R2.1");+    assert_eq!(p.at, (127.0, 50.8));+    assert_eq!(dir_name(p.out), "left");+    let u1 = s.pins_of("U1").unwrap();+    assert_eq!(u1.len(), 8, "three units: 1,2,3 + 5,6,7 + 4,8");+    assert_eq!(pin(&s, "U1.1").at, (160.02, 81.28));+    assert_eq!(pin(&s, "U1.1").etype, "output");+    assert_eq!(pin(&s, "U1.6").at, (144.78, 111.76));+    assert_eq!(pin(&s, "U1.4").at, (180.34, 102.87));+    assert_eq!(pin(&s, "U1.V+").number, "8");+    assert!(s.find_pin("U1.99").is_err());+    assert!(s.find_pin("U1").is_err());+}++#[test]+fn net_walk_and_touching() {+    let s = sch();+    let all = s.all_pins();+    let (nets, others) = s.net_at(pin(&s, "R1.2").at, &all);+    assert_eq!(nets, vec!["VOUT".to_string()]);+    assert!(others.contains(&"R1.2".to_string()));+    let (nets, others) = s.net_at(pin(&s, "C1.2").at, &all);+    assert_eq!(nets, vec!["GND".to_string()], "the power symbol names the net");+    assert!(others.contains(&"#PWR01.1".to_string()));+    let t = s.touching(pin(&s, "R2.1").at);+    assert_eq!(t["noConnect"], true);+    let t = s.touching(pin(&s, "R1.2").at);+    assert_eq!(t["wires"].as_array().unwrap().len(), 1);+}++#[test]+fn items_lists_every_kind() {+    let s = sch();+    let v = s.items(None);+    assert_eq!(v["wires"].as_array().unwrap().len(), 4);+    assert_eq!(v["buses"].as_array().unwrap().len(), 1);+    assert_eq!(v["junctions"].as_array().unwrap().len(), 1);+    assert_eq!(v["noConnects"].as_array().unwrap().len(), 1);+    assert_eq!(v["texts"][0]["text"], "edit fixture");+    assert_eq!(v["powerSymbols"][0]["net"], "GND");+    let kinds: BTreeSet<String> = v["labels"].as_array().unwrap().iter().map(|l| l["kind"].as_str().unwrap().to_string()).collect();+    assert_eq!(kinds, ["global_label", "label"].iter().map(|s| s.to_string()).collect());+    let only = s.items(Some(&["wires".to_string()]));+    assert_eq!(only.as_object().unwrap().len(), 1);+}++#[test]+fn junction_rule_and_auto_junctions() {+    let mut s = sch();+    assert!(s.junction_needed((110.49, 60.96)), "a T needs a dot");+    assert!(!s.junction_needed((100.33, 60.96)), "a corner does not");+    assert!(!s.junction_needed(pin(&s, "R1.2").at), "a pin with one wire does not");+    // A branch off the middle of the VOUT wire gets a dot; its free end does not.+    let (w, j) = s.add_wire_auto(&[(115.57, 60.96), (115.57, 66.04)]).unwrap();+    assert_eq!(w.len(), 1);+    assert_eq!(j.len(), 1);+    assert_eq!(j[0].1, (115.57, 60.96));+    // A wire running through an existing wire end gets a dot there.+    let (_, j) = s.add_wire_auto(&[(110.49, 76.2), (120.65, 76.2)]).unwrap();+    assert!(j.is_empty());+    let (_, j) = s.add_wire_auto(&[(115.57, 66.04), (115.57, 76.2)]).unwrap();+    assert_eq!(j.iter().map(|x| x.1).collect::<Vec<_>>(), vec![(115.57, 76.2)], "an end on another wire's interior");+    // Adding a dot by hand where one is.+    assert!(s.junction_at((115.57, 60.96)).is_some());+    let txt = s.to_text();+    assert!(txt.contains("\t(junction\n\t\t(at 115.57 60.96)\n\t\t(diameter 0)\n\t\t(color 0 0 0 0)\n\t\t(uuid \""));+    reparse(&s);+}++#[test]+fn delete_wire_prunes_and_split_wire_cuts() {+    let mut s = sch();+    let branch = s.wires_between((110.49, 60.96), (110.49, 71.12));+    assert_eq!(branch.len(), 1);+    let (gone, pruned) = s.delete_wires(&branch).unwrap();+    assert_eq!(gone[0].a, (110.49, 60.96));+    assert_eq!(pruned.len(), 1, "the T dot joins nothing now");+    assert!(s.junction_at((110.49, 60.96)).is_none());+    assert!(s.delete_wires(&["nope".to_string()]).is_err());++    let before = s.wires().len();+    let (a, b, j) = s.split_wire((105.41, 60.96), None, true).unwrap();+    assert_ne!(a, b);+    assert!(j.is_some());+    assert_eq!(s.wires().len(), before + 1);+    let w = s.wires();+    let wa = w.iter().find(|x| x.uuid == a).unwrap();+    let wb = w.iter().find(|x| x.uuid == b).unwrap();+    assert_eq!((wa.a, wa.b), ((100.33, 60.96), (105.41, 60.96)));+    assert_eq!((wb.a, wb.b), ((105.41, 60.96), (120.65, 60.96)));+    assert_eq!(s.split_wire((100.33, 60.96), None, true).unwrap_err().code, "not_on_wire");+    // the net still reaches the label across the cut+    let all = s.all_pins();+    assert_eq!(s.net_at(pin(&s, "R1.2").at, &all).0, vec!["VOUT".to_string()]);+    reparse(&s);+}++#[test]+fn move_every_unit_and_stretch_wires() {+    let mut s = sch();+    let (uuids, _) = s.move_units("U1", (2.54, 0.0), false).unwrap();+    assert_eq!(uuids.len(), 3);+    assert_eq!(pin(&s, "U1.1").at, (162.56, 81.28));+    assert_eq!(pin(&s, "U1.4").at, (182.88, 102.87));+    let u1 = s.components(Some(&["U1".to_string()]));+    let ref_field = u1[0]["fields"].as_array().unwrap().iter().find(|f| f["name"] == "Reference").unwrap().clone();+    assert!(ref_field["at"][0].as_f64().unwrap() > 152.4 + 2.0, "fields move with the anchor");++    // R1 down its own axis: the vertical wire end just follows+    let (_, st) = s.move_units("R1", (0.0, -2.54), true).unwrap();+    assert_eq!(st.wires_moved.len(), 1);+    assert!(st.wires_added.is_empty());+    assert_eq!(s.touching(pin(&s, "R1.2").at)["wires"].as_array().unwrap().len(), 1);+    // R1 sideways: the vertical wire stays vertical and a horizontal dogleg joins the pin+    let (_, st) = s.move_units("R1", (5.08, 0.0), true).unwrap();+    assert_eq!(st.wires_added.len(), 1);+    let p2 = pin(&s, "R1.2").at;+    assert_eq!(p2, (105.41, 52.07));+    for w in s.wires() {+        assert!((w.a.0 - w.b.0).abs() < 1e-6 || (w.a.1 - w.b.1).abs() < 1e-6, "every wire stays horizontal or vertical: {w:?}");+    }+    let all = s.all_pins();+    assert_eq!(s.net_at(p2, &all).0, vec!["VOUT".to_string()], "still on its net");++    // The no-connect on R2.1 travels with the pin+    let (_, st) = s.move_units("R2", (0.0, 2.54), true).unwrap();+    assert_eq!(st.flags_moved.len(), 1);+    assert_eq!(s.touching(pin(&s, "R2.1").at)["noConnect"], true);+    assert!(s.move_units("R99", (1.0, 1.0), false).is_err());+    reparse(&s);+}++#[test]+fn rotate_turns_units_and_fields() {+    let mut s = sch();+    let (old, new, uuids) = s.rotate_units("R2", 0.0).unwrap();+    assert_eq!((old, new, uuids.len()), (90.0, 0.0, 1));+    assert_eq!(pin(&s, "R2.1").at, (130.81, 46.99), "pin 1 back on top");+    let (_, _, u) = s.rotate_units("U1", 180.0).unwrap();+    assert_eq!(u.len(), 3);+    assert_eq!(pin(&s, "U1.1").at, (144.78, 81.28), "the output now on the left");+    assert_eq!(pin(&s, "U1.4").at, (185.42, 87.63), "unit 3 turned about its own anchor");+    assert!(s.rotate_units("R2", 45.0).is_err());+    // fields turn about the anchor: a field 2.54 right of R1 ends up 2.54 above after 90+    let before = s.components(Some(&["R1".to_string()]));+    let f = |c: &Vec<serde_json::Value>, n: &str| -> (f64, f64) {+        let f = c[0]["fields"].as_array().unwrap().iter().find(|f| f["name"] == n).unwrap().clone();+        (f["at"][0].as_f64().unwrap(), f["at"][1].as_f64().unwrap())+    };+    let (vx, vy) = f(&before, "Value");+    s.rotate_units("R1", 90.0).unwrap();+    let after = s.components(Some(&["R1".to_string()]));+    let (ax, ay) = f(&after, "Value");+    let (dx, dy) = (vx - 100.33, vy - 50.8);+    assert!(((ax - 100.33) - dy).abs() < 1e-3 && ((ay - 50.8) + dx).abs() < 1e-3, "({vx},{vy}) -> ({ax},{ay})");+    // mirrored: the stored angle runs the other way+    let txt = s.to_text().replacen("(lib_id \"Device:C\")\n\t\t(at 100.33 81.28 0)", "(lib_id \"Device:C\")\n\t\t(at 100.33 81.28 0)\n\t\t(mirror x)", 1);+    let mut m = Schematic::parse(&txt).unwrap();+    m.rotate_units("C1", 90.0).unwrap();+    assert!(m.to_text().contains("(lib_id \"Device:C\")\n\t\t(at 100.33 81.28 90)\n\t\t(mirror x)"));+    reparse(&s);+}++#[test]+fn region_move_takes_what_is_inside() {+    let mut s = sch();+    let moved = s.move_region([45.0, 95.0, 70.0, 130.0], (0.0, -12.7), true, true, true);+    assert_eq!(moved["symbols"].as_array().unwrap().len(), 3, "two R? and the C?");+    assert!(moved.get("wires").is_none());+    let moved = s.move_region([95.0, 55.0, 125.0, 75.0], (0.0, 2.54), true, true, true);+    assert!(moved["wires"].as_array().unwrap().len() >= 2);+    assert_eq!(moved["junctions"].as_array().unwrap().len(), 1);+    assert_eq!(moved["labels"].as_array().unwrap().len(), 2);+    // the wire from R1.2 stretched: its pin end stayed, its other end moved+    assert!(s.touching(pin(&s, "R1.2").at)["wires"].as_array().unwrap().len() == 1);+    reparse(&s);+}++#[test]+fn annotate_numbers_question_marks_like_eeschema() {+    let s = sch();+    let used = s.references_used();+    let plan = s.annotate_plan(&used, false);+    let got: Vec<(String, String, u32)> = plan.iter().map(|p| (p.from.clone(), p.to.clone(), p.unit)).collect();+    assert_eq!(+        got,+        vec![+            ("R?".into(), "R3".into(), 1), // x 50.8 first+            ("C?".into(), "C2".into(), 1),+            ("R?".into(), "R4".into(), 1),+            ("U?".into(), "U2".into(), 1),+            ("U?".into(), "U2".into(), 2), // the second unit packs into the same part+        ]+    );+    // numbers used on other sheets are skipped+    let mut more = used.clone();+    more.insert("R3".into());+    more.insert("U2".into());+    let plan = s.annotate_plan(&more, false);+    assert_eq!(plan[0].to, "R4");+    assert_eq!(plan[3].to, "U3");+    // by y: the C? (y 127) comes after both R? (y 101.6)+    let plan = s.annotate_plan(&used, true);+    assert_eq!(plan.iter().map(|p| p.to.as_str()).collect::<Vec<_>>(), vec!["R3", "R4", "C2", "U2", "U2"]);+    // apply+    let mut s = s;+    for p in &plan {+        s.set_unit_reference(&p.uuid, &p.to).unwrap();+    }+    let again = reparse(&s);+    assert!(again.components(None).iter().all(|c| !c["reference"].as_str().unwrap().ends_with('?')));+    assert!(again.to_text().contains("(reference \"U2\")"));+    assert_eq!(again.unit_indices("U2").len(), 2);+}++#[test]+fn project_sheets_follow_the_hierarchy() {+    let dir = temp_dir("sheets");+    let root = dir.join("proj.kicad_sch");+    let sub = dir.join("sub.kicad_sch");+    std::fs::write(dir.join("proj.kicad_pro"), "{}").unwrap();+    let sheet = "\t(sheet\n\t\t(at 50 50)\n\t\t(size 20 20)\n\t\t(uuid \"aaaaaaaa-0000-4000-8000-000000000001\")\n\t\t(property \"Sheetname\" \"sub\"\n\t\t\t(at 50 49 0)\n\t\t)\n\t\t(property \"Sheetfile\" \"sub.kicad_sch\"\n\t\t\t(at 50 71 0)\n\t\t)\n\t)\n";+    let mut t = fixture();+    t.insert_str(t.find("\t(sheet_instances").unwrap(), sheet);+    std::fs::write(&root, &t).unwrap();+    // the sub-sheet already uses R3+    let subtext = fixture().replace("\"R1\"", "\"R3\"");+    std::fs::write(&sub, subtext).unwrap();+    let sheets = project_sheets(&sub);+    assert_eq!(sheets.len(), 2, "{sheets:?}");+    let s = Schematic::load(&root).unwrap();+    let mut used = s.references_used();+    used.extend(Schematic::load(&sub).unwrap().references_used());+    assert_eq!(s.annotate_plan(&used, false)[0].to, "R4");+    let items = s.items(Some(&["sheets".to_string()]));+    assert_eq!(items["sheets"][0]["file"], "sub.kicad_sch");+    let _ = std::fs::remove_dir_all(&dir);+}++#[test]+fn replace_symbol_keeps_place_and_guards_pins() {+    let mut s = sch();+    let small = minilib("R_Small");+    let r = s.replace_symbol("R1", "Device:R_Small", Some(&small), false).unwrap();+    assert_eq!(r.old_lib_id, "Device:R");+    assert!(r.lib_symbol_added);+    assert!(r.pins_removed.is_empty());+    assert!(!r.old_entry_pruned, "R2 still uses Device:R");+    let c = s.components(Some(&["R1".to_string()]));+    assert_eq!(c[0]["libId"], "Device:R_Small");+    assert_eq!(c[0]["value"], "10k");+    assert_eq!(c[0]["units"][0]["at"], serde_json::json!([100.33, 50.8]));+    // R_Small's pins are 2.54 from the anchor, so pin 2 moved off the wire+    assert_eq!(pin(&s, "R1.2").at, (100.33, 53.34));++    // A one-pin symbol would lose pin 2 of C1+    let one = parse_node("(symbol \"One\" (property \"Reference\" \"TP\" (at 0 0 0) (effects (font (size 1.27 1.27)))) (property \"Value\" \"One\" (at 0 0 0) (effects (font (size 1.27 1.27)))) (symbol \"One_1_1\" (pin passive line (at 0 0 90) (length 0) (name \"1\" (effects (font (size 1.27 1.27)))) (number \"1\" (effects (font (size 1.27 1.27)))))))").unwrap();+    let e = s.replace_symbol("C1", "Test:One", Some(&one), false).unwrap_err();+    assert_eq!(e.code, "pins_lost");+    assert!(!s.has_lib_symbol("Test:One"), "a refusal changes nothing");+    let r = s.replace_symbol("C1", "Test:One", Some(&one), true).unwrap();+    assert_eq!(r.pins_removed, vec!["2".to_string()]);+    assert!(!r.old_entry_pruned, "C? still uses Device:C");+    assert!(s.has_lib_symbol("Device:C"));+    let r = s.replace_symbol("C?", "Test:One", None, true).unwrap();+    assert!(r.old_entry_pruned, "now nothing uses Device:C");+    assert!(!s.has_lib_symbol("Device:C"));+    // a three-unit part cannot become a one-unit resistor+    assert_eq!(s.replace_symbol("U1", "Device:R", None, false).unwrap_err().code, "unit_missing");+    reparse(&s);+}++#[test]+fn update_from_library_detects_changes() {+    let mut s = sch();+    // the fixture was built from these very libraries: nothing to do+    assert!(s.update_lib_symbol("Device:R", &minilib("R"), false).unwrap().is_none());+    let lm = minilib("LM358");+    assert!(s.update_lib_symbol("Amplifier_Operational:LM358", &lm, false).unwrap().is_none(), "flattened extends compares equal");+    // a changed description is an update+    let mut changed = minilib("R");+    let text = changed.to_text().replace("\"Resistor\"", "\"Resistor, updated\"");+    changed = parse_node(&text).unwrap();+    let sync = s.update_lib_symbol("Device:R", &changed, false).unwrap().unwrap();+    assert!(sync.added.is_empty() && sync.removed.is_empty());+    assert!(s.to_text().contains("\"Resistor, updated\""));+    // a library version that drops pin 2 is refused unless forced+    let one = parse_node(&minilib("R").to_text().replacen("(number \"2\"", "(number \"9\"", 1)).unwrap();+    assert_eq!(s.update_lib_symbol("Device:R", &one, false).unwrap_err().code, "pins_lost");+    let sync = s.update_lib_symbol("Device:R", &one, true).unwrap().unwrap();+    assert_eq!(sync.removed, vec!["2".to_string()]);+    assert_eq!(sync.added, vec!["9".to_string()]);+    assert_eq!(s.lib_symbol_keys().len(), 4);+    reparse(&s);+}++#[test]+fn reset_fields_uses_library_offsets() {+    let mut s = sch();+    let done = s.reset_fields("R2", &["Reference".to_string(), "Value".to_string()]).unwrap();+    assert_eq!(done, vec!["1:Reference".to_string(), "1:Value".to_string()]);+    let c = s.components(Some(&["R2".to_string()]));+    let r = c[0]["fields"].as_array().unwrap().iter().find(|f| f["name"] == "Reference").unwrap().clone();+    // Device:R puts Reference at (2.032, 0) angle 90; R2 is turned 90, so it lands 2.032 above+    assert_eq!(r["at"], serde_json::json!([130.81, 48.768]));+    assert_eq!(r["angle"], 90.0);+    let done = s.reset_fields("U1", &["Reference".to_string()]).unwrap();+    assert_eq!(done.len(), 3);+    reparse(&s);+}++#[test]+fn labels_rotate_with_justify() {+    let mut s = sch();+    let idx = s.label_indices(None, Some("VOUT"), Some((120.65, 60.96)));+    assert_eq!(idx.len(), 1);+    s.set_label_rotation(idx[0], 180.0).unwrap();+    let txt = s.to_text();+    assert!(txt.contains("(label \"VOUT\"\n\t\t(at 120.65 60.96 180)\n\t\t(effects\n\t\t\t(font\n\t\t\t\t(size 1.27 1.27)\n\t\t\t)\n\t\t\t(justify right bottom)\n\t\t)"), "{txt}");+    let g = s.label_indices(None, Some("SDA"), None);+    s.set_label_rotation(g[0], 270.0).unwrap();+    assert!(s.to_text().contains("(at 63.5 60.96 270)\n\t\t(fields_autoplaced yes)\n\t\t(effects\n\t\t\t(font\n\t\t\t\t(size 1.27 1.27)\n\t\t\t)\n\t\t\t(justify right)\n\t\t)"));+    assert_eq!(s.label_indices(None, Some("VOUT"), None).len(), 2);+    assert!(s.set_label_rotation(idx[0], 10.0).is_err());+    reparse(&s);+}++#[test]+fn text_bus_and_entries() {+    let mut s = sch();+    let u = s.add_text("Hello\nworld", (25.4, 25.4), 0.0, 2.54, &["left".into(), "bottom".into()], true, false).unwrap();+    let txt = s.to_text();+    assert!(txt.contains(&format!("\t(text \"Hello\\nworld\"\n\t\t(exclude_from_sim no)\n\t\t(at 25.4 25.4 0)\n\t\t(effects\n\t\t\t(font\n\t\t\t\t(size 2.54 2.54)\n\t\t\t\t(bold yes)\n\t\t\t)\n\t\t\t(justify left bottom)\n\t\t)\n\t\t(uuid \"{u}\")\n\t)")), "{txt}");+    assert!(s.add_text("x", (0.0, 0.0), 0.0, 1.27, &["middle".into()], false, false).is_err());+    let b = s.add_segments("bus", &[(220.98, 50.8), (220.98, 76.2)]).unwrap();+    assert_eq!(b.len(), 1);+    let e = s.add_bus_entry((218.44, 63.5), (2.54, -2.54)).unwrap();+    assert!(s.to_text().contains(&format!("\t(bus_entry\n\t\t(at 218.44 63.5)\n\t\t(size 2.54 -2.54)\n\t\t(stroke\n\t\t\t(width 0)\n\t\t\t(type default)\n\t\t)\n\t\t(uuid \"{e}\")\n\t)")));+    assert!(s.add_bus_entry((0.0, 0.0), (0.0, 2.54)).is_err());+    let items = s.items(Some(&["busEntries".to_string(), "buses".to_string()]));+    assert_eq!(items["busEntries"][0]["to"], serde_json::json!([220.98, 60.96]));+    assert_eq!(items["buses"].as_array().unwrap().len(), 2);+    reparse(&s);+}++fn service_kicad() -> Option<PathBuf> {+    let path = std::env::var_os("PATH")?;+    std::env::split_paths(&path).map(|d| d.join("service-kicad")).find(|p| p.is_file())+}++/// KiCad 10 loads a sheet edited by every operation above, and the pins wired by the+/// edits are no longer reported unconnected.+#[test]+fn service_kicad_erc_accepts_an_edited_kicad_10_sheet() {+    let Some(svc) = service_kicad() else {+        eprintln!("service-kicad not on PATH; skipping the live ERC test");+        return;+    };+    let dir = temp_dir("erc");+    let path = dir.join("edit10.kicad_sch");+    let mut s = sch();+    // wire U1.1 (out, right) to R2.2 with an L, flag U1.2/U1.3, stub U1.8 to a label+    let a = pin(&s, "U1.1");+    let b = pin(&s, "R2.2");+    s.add_wire_auto(&l_route(a.at, a.out, b.at, None)).unwrap();+    for p in ["U1.2", "U1.3"] {+        let at = pin(&s, p).at;+        s.add_no_connect(at).unwrap();+    }+    let p8 = pin(&s, "U1.8");+    let end = (p8.at.0 + p8.out.0 * 2.54, p8.at.1 + p8.out.1 * 2.54);+    s.add_wire_auto(&[p8.at, end]).unwrap();+    s.add_label("VCC", LabelKind::Local, end, label_rotation_for(p8.out), None).unwrap();+    s.move_units("C1", (0.0, 2.54), true).unwrap();+    s.rotate_units("R?", 90.0).ok();+    s.add_text("checked by KiCad 10", (50.8, 25.4), 0.0, 1.27, &[], false, false).unwrap();+    let plan = s.annotate_plan(&s.references_used(), false);+    for p in &plan {+        s.set_unit_reference(&p.uuid, &p.to).unwrap();+    }+    std::fs::write(&path, s.to_text()).unwrap();+    let report = dir.join("erc.json");+    let out = Command::new(&svc).args(["sch", "erc"]).arg(&path).args(["--format", "json", "--out"]).arg(&report).output().expect("service-kicad runs");+    assert!(report.is_file(), "service-kicad sch erc wrote no report: {}", String::from_utf8_lossy(&out.stderr));+    let rep: serde_json::Value = serde_json::from_str(&std::fs::read_to_string(&report).unwrap()).unwrap();+    assert!(rep["kicad_version"].as_str().unwrap_or("").starts_with("10"), "KiCad 10 checked it: {}", rep["kicad_version"]);+    let flat = kicad_core::cli::flatten_violations(&rep);+    let unconnected: Vec<String> = flat.iter().filter(|v| v["type"] == "pin_not_connected").map(|v| serde_json::to_string(&v["items"]).unwrap()).collect();+    for p in ["U1 Pin 1 ", "U1 Pin 2 ", "U1 Pin 3 ", "U1 Pin 8 ", "R2 Pin 2 ", "C1 Pin 2 "] {+        assert!(!unconnected.iter().any(|u| u.contains(p)), "{p} still unconnected: {unconnected:?}");+    }+    assert!(!serde_json::to_string(&rep).unwrap().contains("Symbol R?"), "annotated");+    let _ = std::fs::remove_dir_all(&dir);+}

rust/crates/kicad-core/tests/sch_hier.rsadded+344

@@ -0,0 +1,344 @@+//! Schematic hierarchy, connectivity, checks and review on the KiCad 10 fixture project in+//! tests/fixtures/sch_hier: hier.kicad_sch (root) with sheets Power and MCU, and Filter nested+//! in Power (2 levels), plus checks.kicad_sch with one of each connectivity defect. The+//! fixtures were written by eeschema-format code and loaded by KiCad 10.0.2 (service-kicad ERC+//! and SVG export) before being committed. When `service-kicad` is on PATH, files these+//! modules write are run through KiCad 10's ERC too.++use std::path::{Path, PathBuf};+use std::process::Command;++use kicad_core::netlist::parse_kicadxml;+use kicad_core::sch_check::{self, CheckOpts};+use kicad_core::sch_hier::{self, Hierarchy, Paper, TitleEdit};+use kicad_core::sch_model::{self, Connectivity, Item};+use kicad_core::sch_review;+use kicad_core::sch_sheets::Workspace;+use kicad_core::schematic::{new_uuid, Schematic};++fn fixtures() -> PathBuf {+    Path::new(env!("CARGO_MANIFEST_DIR")).join("tests/fixtures/sch_hier")+}++fn copy_project(tag: &str) -> PathBuf {+    let d = std::env::temp_dir().join(format!("kc-schhier-{tag}-{}-{}", std::process::id(), new_uuid()));+    std::fs::create_dir_all(&d).unwrap();+    for e in std::fs::read_dir(fixtures()).unwrap().flatten() {+        std::fs::copy(e.path(), d.join(e.file_name())).unwrap();+    }+    d+}++#[test]+fn fixtures_round_trip_byte_identical() {+    for f in ["hier", "power", "filter", "mcu", "checks"] {+        let p = fixtures().join(format!("{f}.kicad_sch"));+        let text = std::fs::read_to_string(&p).unwrap();+        let s = Schematic::parse(&text).unwrap();+        assert_eq!(s.to_text(), text, "{f} round trip");+        assert_eq!(s.version().unwrap(), sch_hier::SCH_VERSION);+    }+}++#[test]+fn hierarchy_walks_two_levels() {+    let h = Hierarchy::load(&fixtures().join("hier.kicad_sch")).unwrap();+    let human: Vec<&str> = h.instances.iter().map(|i| i.human.as_str()).collect();+    assert_eq!(human, vec!["/", "/Power/", "/Power/Filter/", "/MCU/"]);+    let pages: Vec<&str> = h.instances.iter().map(|i| i.page.as_deref().unwrap_or("")).collect();+    assert_eq!(pages, vec!["1", "2", "3", "4"]);+    assert_eq!(h.docs.len(), 4);+    let filter = &h.instances[2];+    assert_eq!(filter.depth, 2);+    assert_eq!(filter.path.matches('/').count(), 3);+    // the instance path is what the child's symbols carry+    let fs = h.sch(2).unwrap();+    let m = sch_model::extract(fs, Some(&filter.path));+    assert!(m.symbols.iter().any(|s| s.reference == "D1"));+    assert!(h.references().contains("U2"));+    assert_eq!(h.project_name(), "hier");+    assert_eq!(sch_hier::project_root_for(&fixtures().join("mcu.kicad_sch")).unwrap(), fixtures().join("hier.kicad_sch"));+}++#[test]+fn pins_of_rotated_and_mirrored_symbols() {+    let s = Schematic::load(&fixtures().join("checks.kicad_sch")).unwrap();+    let m = sch_model::extract(&s, None);+    // R2 is placed at 90 degrees: its pins run horizontally+    let r2: Vec<(&str, (f64, f64))> = m.pins.iter().filter(|p| p.reference == "R2").map(|p| (p.number.as_str(), p.at)).collect();+    assert_eq!(r2, vec![("1", (72.39, 46.99)), ("2", (80.01, 46.99))]);+    // the regulator's pins carry their electrical types from lib_symbols+    let en = m.pins.iter().find(|p| p.reference == "U1" && p.number == "3").unwrap();+    assert_eq!((en.name.as_str(), en.electrical.as_str()), ("EN", "input"));+    let gnd = m.pins.iter().find(|p| p.reference == "#PWR02").unwrap();+    assert!(gnd.power_symbol);+    assert_eq!(gnd.power_net.as_deref(), Some("GND"));+    let r4 = m.symbols.iter().find(|s| s.reference == "R4").unwrap().bbox.unwrap();+    assert!((r4.1 - 46.99).abs() < 1e-6 && (r4.3 - 54.61).abs() < 1e-6, "{r4:?}");+}++/// Connectivity rules on small hand-written KiCad 10 sheets.+fn sheet(body: &str) -> Schematic {+    let (blank, _) = sch_hier::blank_sheet(&Paper::parse("A4", None, None, false).unwrap(), &TitleEdit::default());+    let text = blank.replacen("\t(sheet_instances", &format!("{body}\t(sheet_instances"), 1);+    Schematic::parse(&text).unwrap()+}++fn wire(a: (f64, f64), b: (f64, f64)) -> String {+    format!("\t(wire\n\t\t(pts\n\t\t\t(xy {} {}) (xy {} {})\n\t\t)\n\t\t(uuid \"{}\")\n\t)\n", a.0, a.1, b.0, b.1, new_uuid())+}++fn label(t: &str, at: (f64, f64)) -> String {+    format!("\t(label \"{t}\"\n\t\t(at {} {} 0)\n\t\t(uuid \"{}\")\n\t)\n", at.0, at.1, new_uuid())+}++fn junction(at: (f64, f64)) -> String {+    format!("\t(junction\n\t\t(at {} {})\n\t\t(diameter 0)\n\t\t(uuid \"{}\")\n\t)\n", at.0, at.1, new_uuid())+}++#[test]+fn connectivity_rules() {+    // a T: a wire end on another wire's interior joins it; a label anywhere on a wire names it+    let s = sheet(&[wire((0.0, 0.0), (20.0, 0.0)), wire((10.0, 0.0), (10.0, 10.0)), label("A", (5.0, 0.0))].concat());+    let m = sch_model::extract(&s, None);+    let c = Connectivity::build(&m);+    assert_eq!(c.of[&Item::Wire(0)], c.of[&Item::Wire(1)]);+    assert_eq!(c.net_name(&m, c.of[&Item::Wire(1)]), "A");+    // a crossing without a junction does not connect; with one it does+    let s = sheet(&[wire((0.0, 0.0), (20.0, 0.0)), wire((10.0, -10.0), (10.0, 10.0))].concat());+    let m = sch_model::extract(&s, None);+    let c = Connectivity::build(&m);+    assert_ne!(c.of[&Item::Wire(0)], c.of[&Item::Wire(1)]);+    let t = sch_check::trace_point(&m, &c, (10.0, 0.0), 0.05);+    assert_eq!(t["crossingWithoutJunction"], true);+    let s = sheet(&[wire((0.0, 0.0), (20.0, 0.0)), wire((10.0, -10.0), (10.0, 10.0)), junction((10.0, 0.0))].concat());+    let m = sch_model::extract(&s, None);+    let c = Connectivity::build(&m);+    assert_eq!(c.of[&Item::Wire(0)], c.of[&Item::Wire(1)]);+    // same-named local labels join two separate wires+    let s = sheet(&[wire((0.0, 0.0), (10.0, 0.0)), wire((0.0, 20.0), (10.0, 20.0)), label("N", (0.0, 0.0)), label("N", (10.0, 20.0))].concat());+    let m = sch_model::extract(&s, None);+    let c = Connectivity::build(&m);+    assert_eq!(c.of[&Item::Wire(0)], c.of[&Item::Wire(1)]);+    assert!(sch_check::dangling_ends(&m).len() == 2, "the far ends dangle");+}++#[test]+fn a_pin_mid_wire_needs_a_junction() {+    // the fixture's R6 and R7 sit mid-wire WITH junctions: both are on NETA+    let s = Schematic::load(&fixtures().join("checks.kicad_sch")).unwrap();+    let m = sch_model::extract(&s, None);+    let c = Connectivity::build(&m);+    let pin = |r: &str, n: &str| m.pins.iter().position(|p| p.reference == r && p.number == n).unwrap();+    assert_eq!(c.of[&Item::Pin(pin("R6", "1"))], c.of[&Item::Pin(pin("R7", "1"))]);+    // drop the junctions: the pins fall off the wire+    let text = std::fs::read_to_string(fixtures().join("checks.kicad_sch")).unwrap();+    let mut s2 = Schematic::parse(&text).unwrap();+    let js: Vec<String> = m.junctions.iter().map(|j| j.uuid.clone()).collect();+    for u in js {+        s2.delete(&u).unwrap();+    }+    let m2 = sch_model::extract(&s2, None);+    let c2 = Connectivity::build(&m2);+    let wire_net = c2.of[&Item::Wire(m2.wires.iter().position(|w| w.a == (50.8, 76.2)).unwrap())];+    assert_ne!(c2.of[&Item::Pin(pin("R6", "1"))], wire_net);+}++#[test]+fn check_on_the_defect_sheet() {+    let s = Schematic::load(&fixtures().join("checks.kicad_sch")).unwrap();+    let m = sch_model::extract(&s, None);+    let c = Connectivity::build(&m);+    let r = sch_check::check(&m, &c, &CheckOpts { overlaps: true });+    let count = |k: &str| r.findings.iter().filter(|f| f.check == k).count();+    assert_eq!(count("dangling_wire_end"), 2);+    assert_eq!(count("floating_label"), 1);+    assert_eq!(count("unconnected_pin"), 1);+    assert_eq!(count("shorted_nets"), 1);+    assert_eq!(count("single_pin_net"), 3);+    assert!(count("overlap") >= 2);+    // the regulator's nets carry power names, so they are judged cross-sheet, not flagged+    assert_eq!(r.cross_sheet_skipped, 3);+    // the power sheet: +3V3 next to the VOUT hierarchical label is a soft "multiple names"+    let s = Schematic::load(&fixtures().join("power.kicad_sch")).unwrap();+    let m = sch_model::extract(&s, None);+    let c = Connectivity::build(&m);+    let r = sch_check::check(&m, &c, &CheckOpts::default());+    let sh: Vec<_> = r.findings.iter().filter(|f| f.check == "shorted_nets").collect();+    assert_eq!(sh.len(), 1);+    assert_eq!(sh[0].severity, "warning");+    assert_eq!(sh[0].nets, vec!["+3V3", "VOUT"]);+}++#[test]+fn two_rails_on_one_wire_are_an_error() {+    let s = sheet(&[+        wire((0.0, 0.0), (20.0, 0.0)),+        "\t(global_label \"+5V\"\n\t\t(shape input)\n\t\t(at 0 0 180)\n\t\t(uuid \"g1\")\n\t)\n".to_string(),+        "\t(global_label \"+3V3\"\n\t\t(shape input)\n\t\t(at 20 0 0)\n\t\t(uuid \"g2\")\n\t)\n".to_string(),+    ]+    .concat());+    let m = sch_model::extract(&s, None);+    let c = Connectivity::build(&m);+    let r = sch_check::check(&m, &c, &CheckOpts::default());+    let f = r.findings.iter().find(|f| f.check == "shorted_nets").unwrap();+    assert_eq!(f.severity, "error");+}++#[test]+fn fix_plan_and_apply_round_trip() {+    let mut s = Schematic::load(&fixtures().join("checks.kicad_sch")).unwrap();+    let m = sch_model::extract(&s, None);+    let (moves, left) = sch_check::plan_fixes(&m, 0.5);+    assert_eq!(moves.len(), 1);+    assert_eq!(left.len(), 1);+    assert!(!moves[0].diagonal);+    assert_eq!(sch_check::apply_moves(&mut s, &moves), 1);+    let s2 = Schematic::parse(&s.to_text()).unwrap();+    let m2 = sch_model::extract(&s2, None);+    assert_eq!(sch_check::dangling_ends(&m2).len(), 1);+    // a tolerance too tight to reach finds nothing+    assert!(sch_check::plan_fixes(&m, 0.2).0.is_empty());+}++#[test]+fn review_from_the_hierarchy() {+    let h = Hierarchy::load(&fixtures().join("hier.kicad_sch")).unwrap();+    let m = sch_review::from_hierarchy(&h);+    assert_eq!(m.sheets, 4);+    // nets join across the hierarchy: the root's VOUT-to-VDD wire, +3V3 and the MCU's VDD are one+    let u2_vdd = m.parts.iter().find(|p| p.reference == "U2").unwrap().pins.iter().find(|p| p.number == "8").unwrap();+    assert_eq!(u2_vdd.net, "+3V3");+    let j2 = m.parts.iter().find(|p| p.reference == "J2").unwrap();+    assert_eq!(j2.pins[0].net, "/MCU/SDA");+    let d1 = m.parts.iter().find(|p| p.reference == "D1").unwrap();+    assert!(d1.pins.iter().any(|p| p.net == "+5V"), "VIN in Filter is +5V through the sheet pin");+    let f = sch_review::review(&m, None);+    let checks: Vec<&str> = f.iter().map(|x| x.check).collect();+    for want in ["decoupling", "i2c_pullups", "reset_enable", "led_resistor", "regulator_caps", "bulk_capacitance"] {+        assert!(checks.contains(&want), "missing {want}: {checks:?}");+    }+    assert!(!checks.contains(&"annotation"));+    let s = sch_review::summary(&m, &f);+    assert_eq!(s["errors"], 1);+}++/// The same checks on kicad-cli's netlist shape (canned kicadxml, as kicad-cli 10 writes it).+#[test]+fn review_from_a_kicad_cli_netlist() {+    let xml = r#"<?xml version="1.0" encoding="UTF-8"?>+<export version="E">+  <components>+    <comp ref="U1"><value>AP2112K-3.3</value><footprint>Package_TO_SOT_SMD:SOT-23-5</footprint><libsource lib="Regulator_Linear" part="AP2112K-3.3" description="LDO"/></comp>+    <comp ref="C1"><value>10u</value><libsource lib="Device" part="C"/></comp>+    <comp ref="C2"><value>10u</value><libsource lib="Device" part="C"/></comp>+    <comp ref="U2"><value>BME280</value><libsource lib="Sensor" part="BME280"/></comp>+    <comp ref="R1"><value>4k7</value><libsource lib="Device" part="R"/></comp>+    <comp ref="R2"><value>4k7</value><libsource lib="Device" part="R"/></comp>+    <comp ref="C3"><value>100n</value><libsource lib="Device" part="C"/></comp>+    <comp ref="D1"><value>RED</value><libsource lib="Device" part="LED"/></comp>+    <comp ref="R3"><value>1k</value><libsource lib="Device" part="R"/></comp>+    <comp ref="R3"><value>1k</value><libsource lib="Device" part="R"/></comp>+  </components>+  <nets>+    <net code="1" name="+5V"><node ref="U1" pin="1" pinfunction="VIN" pintype="power_in"/><node ref="U1" pin="3" pinfunction="EN" pintype="input"/><node ref="C1" pin="1" pintype="passive"/></net>+    <net code="2" name="GND"><node ref="U1" pin="2" pinfunction="GND" pintype="power_in"/><node ref="C1" pin="2" pintype="passive"/><node ref="C2" pin="2" pintype="passive"/><node ref="U2" pin="1" pinfunction="GND" pintype="power_in"/><node ref="C3" pin="2" pintype="passive"/><node ref="D1" pin="1" pinfunction="K" pintype="passive"/></net>+    <net code="3" name="+3V3"><node ref="U1" pin="5" pinfunction="VOUT" pintype="power_out"/><node ref="C2" pin="1" pintype="passive"/><node ref="U2" pin="8" pinfunction="VDD" pintype="power_in"/><node ref="U2" pin="6" pinfunction="VDDIO" pintype="power_in"/><node ref="R1" pin="2" pintype="passive"/><node ref="R2" pin="2" pintype="passive"/><node ref="C3" pin="1" pintype="passive"/></net>+    <net code="4" name="/SDA"><node ref="U2" pin="3" pinfunction="SDI" pintype="bidirectional"/><node ref="R1" pin="1" pintype="passive"/></net>+    <net code="5" name="/SCL"><node ref="U2" pin="4" pinfunction="SCK" pintype="input"/><node ref="R2" pin="1" pintype="passive"/></net>+    <net code="6" name="Net-(D1-A)"><node ref="D1" pin="2" pinfunction="A" pintype="passive"/><node ref="R3" pin="1" pintype="passive"/></net>+    <net code="7" name="+5V_LED"><node ref="R3" pin="2" pintype="passive"/></net>+  </nets>+</export>"#;+    let n = parse_kicadxml(xml).unwrap();+    let m = sch_review::from_netlist(&n);+    assert_eq!(m.source, "netlist");+    let f = sch_review::review(&m, None);+    let checks: Vec<&str> = f.iter().map(|x| x.check).collect();+    // a good design: decoupled, pulled up, EN tied to VIN, LED limited, caps at the LDO+    for clean in ["decoupling", "i2c_pullups", "reset_enable", "led_resistor", "regulator_caps", "bulk_capacitance"] {+        assert!(!checks.contains(&clean), "{clean} flagged: {:#?}", f);+    }+    // the netlist folds the two R3s into one part: duplicates come from the files+    assert!(f.is_empty(), "{f:#?}");+    let mut m = m;+    m.occurrences.push(("R3".into(), 1, "/ other".into()));+    let f = sch_review::review(&m, Some(&["annotation".to_string()]));+    assert_eq!(f.len(), 1);+    assert!(f[0].message.contains("Reference R3 is used by 2"));+    // the files' occurrences of the fixture: every symbol once+    let h = Hierarchy::load(&fixtures().join("hier.kicad_sch")).unwrap();+    assert_eq!(sch_review::occurrences(&h).len(), 10);+}++#[test]+fn workspace_ops_write_files_that_parse_and_load() {+    let d = copy_project("ws");+    let root = d.join("hier.kicad_sch");+    // add a sheet to a SUB-sheet: the instance path runs through the root+    let mut ws = Workspace::open(&d.join("mcu.kicad_sch"), None).unwrap();+    assert_eq!(ws.paths().len(), 1);+    let v = ws.add_sheet("Debug", "debug.kicad_sch", Some((50.8, 120.65)), None, false).unwrap();+    assert_eq!(v["pages"][0]["page"], "5");+    assert!(v["pages"][0]["path"].as_str().unwrap().starts_with(&ws.paths()[0]));+    let w = ws.commit().unwrap();+    assert_eq!(w.created.len(), 1);+    assert_eq!(w.changed.len(), 1);+    let h = Hierarchy::load(&root).unwrap();+    assert!(h.instances.iter().any(|i| i.human == "/MCU/Debug/" && i.doc.is_some()));+    // commit refuses to overwrite a file it was asked to create+    let mut ws = Workspace::open(&root, None).unwrap();+    ws.add_sheet("Again", "debug2.kicad_sch", None, None, false).unwrap();+    std::fs::write(d.join("debug2.kicad_sch"), "taken").unwrap();+    assert!(ws.commit().is_err());+    assert_eq!(std::fs::read_to_string(d.join("debug2.kicad_sch")).unwrap(), "taken");+    // reuse an existing sheet file: its parts get their own references for the new use+    std::fs::remove_file(d.join("debug2.kicad_sch")).unwrap();+    let mut ws = Workspace::open(&root, None).unwrap();+    let v = ws.add_sheet("Filter2", "filter.kicad_sch", None, None, true).unwrap();+    assert_eq!(v["pinsAdded"][0]["name"], "VIN");+    let renamed: Vec<String> = v["renamed"].as_array().unwrap().iter().map(|r| r["to"].as_str().unwrap().to_string()).collect();+    assert!(renamed.contains(&"D2".to_string()), "{renamed:?}");+    ws.commit().unwrap();+    let h = Hierarchy::load(&root).unwrap();+    let rm = sch_review::from_hierarchy(&h);+    let anno = sch_review::review(&rm, Some(&["annotation".to_string()]));+    assert!(anno.is_empty(), "{anno:#?}");+    for (p, _) in &h.docs {+        Schematic::load(p).unwrap();+    }+    let _ = std::fs::remove_dir_all(&d);+}++fn service_kicad() -> Option<PathBuf> {+    let path = std::env::var_os("PATH")?;+    std::env::split_paths(&path).map(|d| d.join("service-kicad")).find(|p| p.is_file())+}++/// KiCad 10's own verdict on what these modules write: a blank sheet with a custom page and+/// title block, a parent with a new sheet and imported pins, and a duplicated sheet. ERC must+/// produce a report (KiCad refusing a file fails here).+#[test]+fn service_kicad_loads_what_we_write() {+    let Some(svc) = service_kicad() else {+        eprintln!("service-kicad not on PATH; skipping the live KiCad 10 test");+        return;+    };+    let d = copy_project("live");+    let (blank, _) = sch_hier::blank_sheet(&Paper::parse("custom", Some(250.0), Some(180.0), false).unwrap(), &TitleEdit { title: Some("Live".into()), comments: vec![(1, "c1".into())], ..Default::default() });+    std::fs::write(d.join("blank.kicad_sch"), blank).unwrap();+    let mut ws = Workspace::open(&d.join("hier.kicad_sch"), None).unwrap();+    ws.duplicate_sheet("MCU", Some("MCU_B"), None, None).unwrap();+    ws.add_sheet("FilterReuse", "filter.kicad_sch", None, None, true).unwrap();+    ws.add_pin("Power", "EXTRA", "passive", None, None).unwrap();+    ws.commit().unwrap();+    for f in ["blank.kicad_sch", "hier.kicad_sch", "mcu_copy.kicad_sch", "filter.kicad_sch"] {+        let out = d.join(format!("{f}.erc.json"));+        let r = Command::new(&svc).args(["sch", "erc", "--format", "json", "--out"]).arg(&out).arg(d.join(f)).output().expect("service-kicad runs");+        let report = std::fs::read_to_string(&out).unwrap_or_default();+        let v: serde_json::Value = serde_json::from_str(&report).unwrap_or_else(|_| panic!("{f}: KiCad 10 wrote no ERC report: {}", String::from_utf8_lossy(&r.stderr)));+        assert!(v["kicad_version"].as_str().unwrap_or("").starts_with("10."), "{f}: {v}");+        assert!(v["sheets"].is_array(), "{f}");+    }+    let _ = std::fs::remove_dir_all(&d);+}