# KA3525

**lingxingic** · AC-DC Controllers And Regulators · SOP-16

KA3525 from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EA(-) | input | Error amplifier inverting input. |
| 2 | EA(+) | input | Error amplifier non-inverting input; CMRR is specified for a common-mode voltage of 1.5 V to 5.2 V. |
| 3 | SYNC | input | External synchronous signal input of the oscillator; sync threshold is 1.2 V min, 2 V typ, 2.8 V max. |
| 4 | OSC OUTPUT | output | Oscillator output; clock amplitude is 3 V min and 4 V typ under RT=3.6 kΩ, CT=0.01 µF. |
| 5 | CT | passive | Oscillator timing capacitor access. |
| 6 | RT | passive | Oscillator timing resistor access. |
| 7 | DISCHARGE | passive | Oscillator discharge terminal. |
| 8 | SOFT START | passive | Soft-start capacitor access; soft-start current is 25 µA min, 51 µA typ, 80 µA max. |
| 9 | EA_OUT | input | Input for the PWM relatively strong compensation signal. |
| 10 | SHUTDOWN | input | External shutdown signal input; shutdown threshold is 0.7 V min, 1.3 V typ, 1.7 V max. |
| 11 | OUTPUT A | output | Output A; absolute maximum sink or source output current is 500 mA. |
| 12 | GND | power_in | Signal ground. |
| 13 | VC | power_in | Output stage bias voltage access point; absolute maximum collector supply voltage is 40 V. |
| 14 | OUTPUT B | output | Output B; absolute maximum sink or source output current is 500 mA. |
| 15 | VCC | power_in | Bias power access; absolute maximum supply voltage is 40 V, and electrical characteristics are specified at VCC=20 V. |
| 16 | VREF | power_out | Reference voltage output of 5.0 V min, 5.1 V typ, 5.2 V max at TJ=+25 °C; absolute maximum reference output current is 50 mA. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC |  |  | 40 | V |  | 4 |
| Collector Supply Voltage | VC |  |  | 40 | V |  | 4 |
| Output Current, Sink or Source | IO |  |  | 500 | mA |  | 4 |
| Reference Output Current | IREF |  |  | 50 | mA |  | 4 |
| Oscillator Charging Current | ICHG |  |  | 5 | mA |  | 4 |
| Power Dissipation | PD |  |  | 1000 | mW | Tamb=25℃ | 4 |
| Operating Temperature | Tamb | 0 |  | 70 | ℃ |  | 4 |
| Storage Temperature | Tstg | -65 |  | 150 | ℃ |  | 4 |
| Soldering Temperature | TL |  |  | 250 | ℃ | 10s (SOP) | 4 |
| Frequency Change With Voltage | △f/△VCC | -2 | 0.8 | 2 | % | VCC=8 to 35V, RT=3.6KΩ,CT=0.01uF | 5 |
| Maximum Frequency | f(MAX) | 400 | 430 |  | KHz | RT=2KΩ,CT=470pF | 5 |
| Minimum Frequency | f(MIN) |  | 60 | 120 | Hz | RT=200KΩ,CT=0.1uF | 5 |
| Clock Amplitude | V(CLK) | 3 | 4 |  | V | RT=3.6KΩ,CT=0.01uF | 5 |
| Clock Width | tW(CLK) | 0.3 | 0.6 | 1 | us | RT=3.6KΩ,CT=0.01uF | 5 |
| Sync Threshold | VTH(SYNC) | 1.2 | 2 | 2.8 | V |  | 5 |
| Sync Input Current | II(SYNC) |  | 1.3 | 2.5 | mA | Sync＝3.5V | 5 |
| Input Offset Voltage | VIO |  | 1.5 | 10 | mV |  | 5 |
| Input Bias Current | IBAIS |  | 1 | 10 | uA |  | 5 |
| Input Offset Current | IIO |  | 0.1 | 1 | uA |  | 5 |
| Open Loop Voltage Gain | GVO | 60 | 80 |  | dB | RL10MΩ | 5 |
| Common Mode Rejection Ratio | CMRR | 60 | 90 |  | dB | VCM＝1.5 to 5.2V | 5 |
| Minimum Duty Cycle | D(MIN) |  |  | 0 | % |  | 5 |
| Maximum Duty Cycle | D(MAX) | 45 | 49 |  | % | RT=3.6KΩ,CT=1nF | 5 |
| Input Threshold Voltage (Zero Duty Cycle) | VTH1 | 0.7 | 0.9 |  | V | Zero Duty Cycle, RT=3.6KΩ,CT=0.01uF | 5 |
| Input Threshold Voltage (Max Duty Cycle) | VTH2 |  | 3.2 | 3.6 | V | Max Duty Cycle, RT=3.6KΩ,CT=0.01uF | 5 |
| Soft Start Current | ISOFT | 25 | 51 | 80 | uA | VSD=0V,VSS=0V | 5 |
| Soft Start Low Level Voltage | VSL |  | 0.3 | 0.7 | V | VSD=25V | 5 |
| Shutdown Threshold Voltage | VTH(SD) | 0.7 | 1.3 | 1.7 | V |  | 5 |
| Shutdown Input Current | IN(SD) |  | 0.3 | 1 | mA | VSD=2.5V | 5 |
| Low Output Voltage I | VOL I |  | 0.1 | 0.4 | mV | ISINK=20mA, RT=3.6KΩ,CT=0.1uF | 5 |
| Low Output Voltage II | VOL II |  | 0.05 | 2 | V | ISINK=100mA, RT=3.6KΩ,CT=0.1uF | 5 |
| High Output Voltage I | VOH I | 18 | 19 |  | V | ISOURCE=20mA, RT=3.6KΩ,CT=0.1uF | 5 |
| High Output Voltage II | VOH II | 17 | 18 |  | V | ISOURCE=100mA, RT=3.6KΩ,CT=0.1uF | 5 |
| Reference Output Voltage | VREF | 5 | 5.1 | 5.2 | V | TJ=+25℃ | 5 |
| Line Regulation | △VREF |  | 9 | 20 | mV | VCC=8 to 35V | 5 |
| Load Regulation | △VREF |  | 20 | 50 | mV | IREF=0 to 20mA | 5 |
| Short Circuit Output Current | ISC |  | 80 | 100 | mA | VREF=0V,TJ=+25℃ | 5 |
| Under Voltage Lockout | VUV | 6 | 7 | 8 | V | V8 and V9=High | 6 |
| Rise Time | tR |  | 80 | 600 | us | CL=1nF,TJ=+25℃ | 6 |
| Fall Time | tF |  | 70 | 300 | us | CL=1nF,TJ=+25℃ | 6 |
| Supply Current | ICC |  | 12 | 20 | mA | VCC=35V, RT=3.6KΩ,CT=1nF | 6 |

## CAD (KiCad official)

- Symbol: `KA3525`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `ka3525-etched.step` / `ka3525-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ka3525.step` / `ka3525.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [lingxingic datasheet](docs/ka3525-datasheet.pdf) (9 pp, sha256 `f68044d884e5c414`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ka3525-datasheet.pdf)