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JY1117E18AX
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Shenzhen JingYang Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT223-3L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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JY1117E18AX
Shenzhen JingYang · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT223-3L
JY1117E18AX from Shenzhen JingYang, in a SOT223-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Adj (GND) | power_in | Resistor divider from this pin to VOUT and ground sets the output voltage in the adjustable version, and in the fixed-mode version (JY1117-18 is fixed 1.8V) this pin is ground only. |
| 2 | VOUT | power_out | Regulator output; a minimum 0.2uF X7R or X5R ceramic output capacitor is strongly recommended to prevent oscillation, and a minimum 3.3uF electrolytic capacitor (10mΩ ≤ ESR ≤ 1Ω, up to 100uF) must be connected from this pin to ground for stability. |
| 3 | VIN | power_in | Input pin, typically with a large storage capacitor to ground; it must always be at least 1.5V higher than VOUT for proper regulation, with an operating input range of 2.7V to 12V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Shenzhen JingYang |
| Package | SOT223-3L |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operation Input Voltage | VIN | 2.7 | 12 | V | 4 | ||
| Output Voltage (JY1117-1.8) | VOUT | 1.764 | 1.8 | 1.836 | V | IOUT = 10mA | 4 |
| Line Regulation | 0.2 | 0.5 | % | IOUT=10mA, VOUT+1.5V<VIN<12V, TJ=25°C (Note 1,2) | 4 | ||
| Load Regulation (JY1117-1.8) | 15 | 18 | mV | VIN=3.3V, 0mA≤IOUT≤1A, TJ=25°C (Note 1,2) | 4 | ||
| Dropout Voltage (VIN-VOUT) | 1.2 | 1.4 | V | IOUT = 1A, VOUT=1%VOUT | 5 | ||
| Current Limit | 1 | 1.8 | A | (VIN-VOUT) = 1.5V | 5 | ||
| Minimum Load Current | 5 | 7 | mA | 0°C≤Tj≤125°C | 5 |
CAD (KiCad official)
- Symbol:
JY1117E18AX - Footprint:
Package_TO_SOT_SMD:SOT-223-3_TabPin2 - 3D model: SOT223-3L (KiCad packages3D, STEP)
- 3D model files:
jy1117e18ax-etched.step/jy1117e18ax-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);jy1117e18ax.step/jy1117e18ax.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Shenzhen JingYang datasheet (13 pp, sha256
17cca7e7aa6ec0b8, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# JY1117E18AX
**Shenzhen JingYang** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT223-3L
JY1117E18AX from Shenzhen JingYang, in a SOT223-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Adj (GND) | power_in | Resistor divider from this pin to VOUT and ground sets the output voltage in the adjustable version, and in the fixed-mode version (JY1117-18 is fixed 1.8V) this pin is ground only. |
| 2 | VOUT | power_out | Regulator output; a minimum 0.2uF X7R or X5R ceramic output capacitor is strongly recommended to prevent oscillation, and a minimum 3.3uF electrolytic capacitor (10mΩ ≤ ESR ≤ 1Ω, up to 100uF) must be connected from this pin to ground for stability. |
| 3 | VIN | power_in | Input pin, typically with a large storage capacitor to ground; it must always be at least 1.5V higher than VOUT for proper regulation, with an operating input range of 2.7V to 12V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Shenzhen JingYang |
| Package | SOT223-3L |
| Category | Power Management (PMIC) |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operation Input Voltage | VIN | 2.7 | | 12 | V | | 4 |
| Output Voltage (JY1117-1.8) | VOUT | 1.764 | 1.8 | 1.836 | V | IOUT = 10mA | 4 |
| Line Regulation | | | 0.2 | 0.5 | % | IOUT=10mA, VOUT+1.5V<VIN<12V, TJ=25°C (Note 1,2) | 4 |
| Load Regulation (JY1117-1.8) | | | 15 | 18 | mV | VIN=3.3V, 0mA≤IOUT≤1A, TJ=25°C (Note 1,2) | 4 |
| Dropout Voltage (VIN-VOUT) | | | 1.2 | 1.4 | V | IOUT = 1A, VOUT=1%VOUT | 5 |
| Current Limit | | 1 | | 1.8 | A | (VIN-VOUT) = 1.5V | 5 |
| Minimum Load Current | | | 5 | 7 | mA | 0°C≤Tj≤125°C | 5 |
## CAD (KiCad official)
- Symbol: `JY1117E18AX`
- Footprint: `Package_TO_SOT_SMD:SOT-223-3_TabPin2`
- 3D model: SOT223-3L (KiCad packages3D, STEP)
- 3D model files: `jy1117e18ax-etched.step` / `jy1117e18ax-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `jy1117e18ax.step` / `jy1117e18ax.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Shenzhen JingYang datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603178682244743168) (13 pp, sha256 `17cca7e7aa6ec0b8`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/jy1117e18ax-datasheet.pdf)