# JSM4407

**JSMSEMI** · MOSFETs · SOP-8

JSM4407 from JSMSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the P-channel MOSFET, rated for VDS = -30 V with VGS limited to ±20 V. |
| 2 | S | passive | Source terminal of the P-channel MOSFET, rated for VDS = -30 V with VGS limited to ±20 V. |
| 3 | S | passive | Source terminal of the P-channel MOSFET, rated for VDS = -30 V with VGS limited to ±20 V. |
| 4 | G | input | Gate control input of the P-channel MOSFET; VGS is limited to ±20 V and RDS(on) is specified at VGS = -4.5 V and -10 V. |
| 5 | D | passive | Drain terminal of the P-channel MOSFET; continuous drain current is -10 A at TA = 25 ℃ and pulsed drain current is -60 A. |
| 6 | D | passive | Drain terminal of the P-channel MOSFET; continuous drain current is -10 A at TA = 25 ℃ and pulsed drain current is -60 A. |
| 7 | D | passive | Drain terminal of the P-channel MOSFET; continuous drain current is -10 A at TA = 25 ℃ and pulsed drain current is -60 A. |
| 8 | D | passive | Drain terminal of the P-channel MOSFET; continuous drain current is -10 A at TA = 25 ℃ and pulsed drain current is -60 A. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | JSMSEMI |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | -30 |  |  | V |  | 1 |
| Gate-Source Voltage | VGS | -20 |  | 20 | V |  | 1 |
| Continuous Drain Current | ID | -10 |  |  | A | TJ=150℃, TA=25℃ | 1 |
| Drain Current-Pulsed | IDM | -60 |  |  | A | Note 1 | 1 |
| Maximum Power Dissipation | PD |  |  | 2.1 | W |  | 1 |
| Operating Junction and Storage Temperature Range | TJ,TST | -55 |  |  | ℃ |  | 1 |
| Thermal Resistance, Junction-to-Ambient | RθJA |  |  | 50 | ℃/W | Note 2: surface mounted on FR4 board, t ≤ 10 sec | 1 |
| Drain-Source Breakdown Voltage | BVDSS | -30 |  |  | V | VGS=0V, ID=-250μA | 2 |
| Zero Gate Voltage Drain Current | IDSS |  |  | -1 | μA | VDS=-30V, VGS=0V | 2 |
| Gate-Body Leakage Current | IGSS | -100 |  | 100 | nA | VGS=±20V, VDS=0V | 2 |
| Gate Threshold Voltage | VGS(th) | -1 |  | -3 | V | VDS=VGS, ID=-250μA | 2 |
| Drain-Source On-State Resistance | RDS(ON) |  | 9 | 14 | mΩ | VGS=-10V, ID=-10.0A | 2 |
| Drain-Source On-State Resistance | RDS(ON) |  | 14 | 20 | mΩ | VGS=-4.5V, ID=-6.0A | 2 |
| Forward Transconductance | gFS | 20 |  |  | S | VDS=-15V, ID=-5.0A | 2 |
| Diode Forward Voltage | VSD |  |  | -1.2 | V | VGS=0V, IS=-10A | 2 |

## CAD (KiCad official)

- Symbol: `JSM4407`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `jsm4407-etched.step` / `jsm4407-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `jsm4407.step` / `jsm4407.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [JSMSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590224284901158912) (6 pp, sha256 `aaccfbc40a812c90`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/jsm4407-datasheet.pdf)