# JMTP4435A

**Jiangsu JieJie Microelectronics** · MOSFETs · SOP-8

JMTP4435A from Jiangsu JieJie Microelectronics, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, shown as S on pin 1 in the SOP-8 pin assignment diagram. |
| 2 | S | passive | Source of the P-channel MOSFET, shown as S on pin 2 in the SOP-8 pin assignment diagram. |
| 3 | S | passive | Source of the P-channel MOSFET, shown as S on pin 3 in the SOP-8 pin assignment diagram. |
| 4 | G | input | Gate of the P-channel MOSFET with VGSS rated at ±20V and VGS(th) of -1.0V min to -2.4V max. |
| 5 | D | passive | Drain of the P-channel MOSFET with VDSS of -30V and continuous drain current of -10A at TC=25℃. |
| 6 | D | passive | Drain of the P-channel MOSFET with VDSS of -30V and continuous drain current of -10A at TC=25℃. |
| 7 | D | passive | Drain of the P-channel MOSFET with VDSS of -30V and continuous drain current of -10A at TC=25℃. |
| 8 | D | passive | Drain of the P-channel MOSFET with VDSS of -30V and continuous drain current of -10A at TC=25℃. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Jiangsu JieJie Microelectronics |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS |  |  | -30 | V |  | 1 |
| Gate-Source Voltage | VGSS | -20 |  | 20 | V |  | 1 |
| Continuous Drain Current | ID |  |  | -10 | A | TC = 25℃ | 1 |
| Continuous Drain Current | ID |  |  | -7 | A | TC = 100℃ | 1 |
| Pulsed Drain Current | IDM |  |  | -40 | A | note1 | 1 |
| Power Dissipation | PD |  |  | 3.7 | W | TA = 25℃ | 1 |
| Thermal Resistance, Junction to Ambient | RθJA |  |  | 33.8 | ℃/W |  | 1 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 |  | 150 | ℃ |  | 1 |
| Drain-Source Breakdown Voltage | V(BR)DSS | -30 |  |  | V | VGS=0V, ID=-250μA | 2 |
| Zero Gate Voltage Drain Current | IDSS |  |  | -1 | μA | VDS = -30V, VGS = 0V | 2 |
| Gate to Body Leakage Current | IGSS | -100 |  | 100 | nA | VDS =0V, VGS = ±20V | 2 |
| Gate Threshold Voltage | VGS(th) | -1 | -1.5 | -2.4 | V | VDS= VGS, ID= -250μA | 2 |
| Static Drain-Source on-Resistance | RDS(on) |  | 16 | 23 | mΩ | VGS =-10V, ID =-10A | 2 |
| Static Drain-Source on-Resistance | RDS(on) |  | 25 | 34 | mΩ | VGS =-4.5V, ID =-5A | 2 |
| Maximum Continuous Drain to Source Diode Forward Current | IS |  |  | -10 | A |  | 2 |
| Maximum Pulsed Drain to Source Diode Forward Current | ISM |  |  | -40 | A |  | 2 |
| Drain to Source Diode Forward Voltage | VSD |  | -0.8 | -1.2 | V | VGS = 0V, IS = -10A | 2 |

## CAD (KiCad official)

- Symbol: `JMTP4435A`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `jmtp4435a-etched.step` / `jmtp4435a-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `jmtp4435a.step` / `jmtp4435a.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Jiangsu JieJie Microelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589837065090334720) (6 pp, sha256 `33f3f3d9e716970c`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/jmtp4435a-datasheet.pdf)