component

JFE2140DR

Public Made by Adom

by adom

Texas Instruments Pre-ordered Products, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsolders - accessories - batteriesjfe2140drfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8h ago
viewers jfe2140dr: viewers · Ray 8h ago
jfe2140dr-etched.glb Publish 0.1.0 · Ray 8h ago
jfe2140dr-etched.step jfe2140dr: factory component page (tier=mfr) · Ray 8h ago
jfe2140dr-hero.glb jfe2140dr: hero GLB from the etched model (keeps the MPN mark) · Ray 8h ago
jfe2140dr-hero.overlay.json Publish 0.1.0 · Ray 8h ago
jfe2140dr.glb Publish 0.1.0 · Ray 8h ago
jfe2140dr.kicad_mod Publish 0.1.0 · Ray 8h ago
jfe2140dr.kicad_sym Publish 0.1.0 · Ray 8h ago
jfe2140dr.lbr Publish 0.1.0 · Ray 8h ago
jfe2140dr.step Publish 0.1.0 · Ray 8h ago
package.json Publish 0.1.0 · Ray 8h ago
page.json Set visibility: public · Ray 8h ago
README.md Publish 0.1.0 · Ray 8h ago

JFE2140DR

Texas Instruments · Pre-ordered Products · SOIC-8

JFE2140DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of JFET channel 1.
2 D1 passive Drain of JFET channel 1.
3 VCH passive Positive diode clamp voltage; float this pin if clamp diodes are not used (max 40 V between VCH and D, G, or S).
4 G1 input Gate of JFET channel 1.
5 S2 passive Source of JFET channel 2.
6 D2 passive Drain of JFET channel 2.
7 VCL passive Negative diode clamp voltage; float this pin if clamp diodes are not used (min -40 V between VCL and D, G, or S).
8 G2 input Gate of JFET channel 2.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Solders / Accessories / Batteries
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-to-source voltage VDS -40 40 V 4
Gate-to-source voltage, gate-to-drain voltage VGS, VGD -40 0.1 V 4
Voltage between VCH to D, G, or S VVCH 40 V 4
Voltage between VCL to D, G, or S VVCL -40 V 4
Clamp diode current DC IVCL, IVCH 20 mA DC 4
Clamp diode current pulse IVCL, IVCH 200 mA 50-ms pulse 4
Drain-to-source current IDS -50 50 mA 4
Gate-to-source current, gate-to-drain current IGS, IGD -20 20 mA 4
Ambient temperature TA -55 150 °C 4
Junction temperature TJ -55 150 °C 4
Storage temperature Tstg -55 175 °C 4
ESD HBM V(ESD) -2000 2000 V Human body model, ANSI/ESDA/JEDEC JS-001 4
ESD CDM V(ESD) -500 500 V Charged device model, ANSI/ESDA/JEDEC JS-002 4
Drain-to-source current IDS 0.02 mA max is IDSS 4
Gate-to-source voltage VGS -1.2 0 V 4
Specified temperature TJ -40 125 °C 4
Junction-to-ambient thermal resistance RθJA 139.8 °C/W D (SOIC) 8 pins 4
Junction-to-case (top) thermal resistance RθJC(top) 80 °C/W D (SOIC) 8 pins 4
Junction-to-board thermal resistance RθJB 83.2 °C/W D (SOIC) 8 pins 4
Junction-to-top characterization parameter ψJT 29.1 °C/W D (SOIC) 8 pins 4
Junction-to-board characterization parameter ψJB 82.4 °C/W D (SOIC) 8 pins 4
Input gate current IG -10 1 10 pA VDS = 2 V, VVCH = 5 V, VVCL = -5 V 5
Input gate current IG -60 0.2 60 pA VDS = 0 V, VGS = -30 V 5
Input gate current IG 0.85 nA TA = -40°C to +85°C 5
Input gate current IG 9 nA TA = -40°C to +125°C 5
Gate-to-source breakdown voltage VGSS -40 V VDS = 0 V, IG = -100 µA 5
Gate-to-source cutoff voltage VGSC -1.5 -1.15 -0.9 V VDS = 10 V, IDS = 0.1 µA 5
Gate-to-source voltage VGS -1.3 -0.85 -0.7 V IDS = 100 µA 5
Gate-to-source voltage VGS -1.1 -0.6 -0.5 V IDS = 2 mA 5
Differential VGS mismatch ΔVGS 1 4 mV IDS = 2 mA 5
Differential VGS mismatch ΔVGS 1.1 4.2 mV TA = -40°C to +125°C 5
Differential VGS mismatch drift -10 1.7 10 µV/°C TA = -40°C to +125°C 5
Gate input resistance RIN 1 TΩ VGS = -30 V to -1 V, VDS = 0 V 5
Drain-to-source saturation current IDSS 12 18 23 mA VGS = 0 V 5
Drain-to-source saturation current IDSS 10 28 mA TA = -40°C to +125°C 5
Drain-to-source saturation current ratio IDSS1 / IDSS2 0.95 1 1.05 VGS = 0 V 5
Full conduction transconductance GFS 24 30 mS VGS = 0 V 5
Drain-to-source breakdown voltage VDSS 40 43 V IDS = 100 µA 5
Input-referred noise en 2.5 nV/√Hz IDS = 100 µA, f = 1 kHz 5
Input-referred noise en 5.4 nV/√Hz IDS = 100 µA, f = 10 Hz 5
Input-referred noise en 0.26 µVPP IDS = 100 µA, f = 0.1 Hz to 10 Hz 5
Input-referred noise en 1.1 nV/√Hz IDS = 2 mA, f = 1 kHz 5
Input-referred noise en 2.4 nV/√Hz IDS = 2 mA, f = 10 Hz 5
Input-referred noise en 0.12 µVPP IDS = 2 mA, f = 0.1 Hz to 10 Hz 5
Input current noise, each input ei 1.6 fA/√Hz f = 1 kHz, IDS = 2 mA, VDS = 5 V 5
Input capacitance CISS 17 pF VDS = 0 V 5
Input capacitance CISS 13 pF VDS = 5 V 5
Transconductance 2.1 mS IDS = 100 µA 5
Transconductance 10 mS IDS = 2 mA 5
Output capacitance COSS 4.5 pF IDS = 2 mA 5

CAD (KiCad official)

  • Symbol: JFE2140DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: jfe2140dr-etched.step / jfe2140dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); jfe2140dr.step / jfe2140dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 baeb38d1596ab468, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF