component
JD6606SSP
Public Made by Adomby adom
JADARD USB ICs, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownJD6606SSP
JADARD · USB ICs · SOP-8-EP
JD6606SSP from JADARD, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Supply input voltage pin; recommended VDD is 3.2V to 6.8V, with an internal shunt clamping VDD at about 6.4V (6.4V typ., 5.9V to 6.8V) and an absolute maximum of 7V. |
| 2 | CSN | input | Negative input of the current sense amplifier, to be Kelvin-connected to the sense resistor. |
| 3 | CSP | input | Positive input of the current sense amplifier, to be Kelvin-connected to the sense resistor and routed differentially with CSN. |
| 4 | FBO | input | Voltage loop feedback input from the output resistor divider used for constant-voltage regulation; absolute maximum rating is -0.3V to +6.5V. |
| 5 | CC1 | bidirectional | Type-C configuration channel signal 1; over-voltage protected, with absolute maximum rating of -0.3V to +24V. |
| 6 | CC2 | bidirectional | Type-C configuration channel signal 2; over-voltage protected, with absolute maximum rating of -0.3V to +24V. |
| 7 | VBUSC | input | VBUS voltage detection for the Type-C connector side, also used for VBUSC discharge; absolute maximum rating is -0.3V to +35V. |
| 8 | GATE | output | N-MOSFET gate drive output controlling the external blocking MOSFET; absolute maximum rating is -0.3V to +35V and it is pulled low on VBUS over-voltage. |
| 9 | GND | power_in | Power ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | JADARD |
| Package | SOP-8-EP |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Voltage (absolute maximum) | VDD | -0.3 | 7 | V | 11 | ||
| CC1, CC2, D-, D+, OPTO voltage | -0.3 | 24 | V | 11 | |||
| GATE, VBUS, VBUSC voltage | -0.3 | 35 | V | 11 | |||
| CSP, CSN voltage | -0.3 | 6.5 | V | 11 | |||
| FBO, IFB, MPC, RPDO voltage | -0.3 | 6.5 | V | 11 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 11 | |||
| Storage Temperature | TS | -65 | 150 | °C | 11 | ||
| Lead Temperature (Soldering) | 260 | °C | 10 sec | 11 | |||
| Input Supply Voltage (recommended) | VDD | 3.2 | 6.8 | V | 11 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | 11 | ||
| Package Thermal Resistance junction-to-ambient SOP-8 EP | θJA | 60 | °C/W | 11 | |||
| Package Thermal Resistance junction-to-case SOP-8 EP | θJC | 15 | °C/W | 11 | |||
| VDD Input Voltage Range | VDD | 3.2 | 6.8 | V | 12 | ||
| VDD Input UVLO Threshold (rising) | VDD_UVLO | 3.1 | 3.3 | 3.5 | V | VDD Rising | 12 |
| VDD Input UVLO Threshold (falling) | VDD_HYS | 2.45 | 2.6 | 2.75 | V | VDD Falling | 12 |
| VDD Supply Current | IDD_SUP | 66 | 100 | 136 | μA | VDD=5V, Nothing Attach | 12 |
| VDD Shunt Voltage | VDD_SHDN | 5.9 | 6.4 | 6.8 | V | 12 | |
| Sourcing Voltage (ON) between GATE and VBUS | 5 | 15 | V | VDD=3.2V to 6.8V | 12 | ||
| VBUS Over Voltage Protection | 22.8 | 24 | 25.2 | V | 12 | ||
| VBUS Bleed Discharge Resistance | R_Bleed | 8 | 10 | 12.5 | kΩ | 12 | |
| VBUSC Bleed Discharge Resistance | R_CBLEED | 8 | 10 | 12.5 | kΩ | 12 | |
| SRC CC Current | ICC_3A | 304 | 330 | 356 | μA | Cable is attached whit Rd, PD Disabled | 12 |
| Data Detect Voltage | VDAT(REF) | 0.25 | 0.325 | 0.4 | V | 13 | |
| Output Voltage Selection Reference | VSEL_REF | 1.8 | 2 | 2.2 | V | 13 | |
| D+ High Glitch Filter Time | TGLITCH(BC)-DPA-H | 1000 | 1250 | 1500 | ms | 13 | |
| Output Voltage Glitch Filter Time | TGLITCH(V)CHANGE | 20 | 40 | 60 | ms | 13 | |
| Continuous Mode Glitch Filter Time | TGLITCH-CONTCHANGE | 100 | 200 | ms | 13 | ||
| D+ Leakage Resistance | RDAT-LKG | 300 | 500 | 800 | kΩ | VDD=3.2 to 6.4V, VDPA=0.6-3.6V Switch SW1=off | 13 |
| D+_0.48V / D-_0.48V Line Output Voltage | 0.44 | 0.48 | 0.52 | V | 13 | ||
| D+_2.7V / D-_2.7V Line Output Voltage | 2.57 | 2.7 | 2.84 | V | 13 | ||
| D- Tx Valid Output High | VTX-VOH | 2.55 | 3.6 | V | 13 | ||
| D- Rx Valid Output High | VRX-VIH | 1.4 | 3.6 | V | 13 | ||
| D- Output Pull-Low Resistance | RPD | 400 | 500 | 600 | Ω | 13 | |
| Unit Interval for PHY Communication | UI | 144 | 160 | 180 | μs | FCLK=125kHz | 13 |
| OPTO Sinking Current | IOPTO | 27 | 80 | mA | 14 | ||
| D+/D- OV Threshold in DCP mode | V_DPDNOV | 7 | V | In DCP mode | 12 | ||
| D+/D- OV Threshold in HVDCP mode | V_DPDNOV | 4 | V | In HVDCP Mode | 12 | ||
| VBUS Discharge Resistance | R_DIS | 400 | Ω | 12 | |||
| VBUSC Discharge Resistance | R_CDIS | 400 | Ω | 12 | |||
| D+ Glitch Filter Time (DNA low) | TGLITCH(BC)-DNA-L | 1 | ms | 13 | |||
| D- Pull-Down Resistance | RDNA(DWN) | 20 | kΩ | 13 | |||
| Switch SW1 On-Resistance | RDS_ON_N1 | 40 | Ω | VDD=5V,SW1=200μA | 13 | ||
| UP/Down Current Step | IUP, IDOWN | 2 | μA | IUP =0μA (5V),40μA (9V), 70μA (12V),100μA (15V),150μA (20V) IDOWN=14μA (3.6V) | 13 | ||
| DCP Charging Mode Line Output Impedance | 900 | kΩ | 13 | ||||
| Apple Mode Line Output Impedance | 33.6 | kΩ | 13 | ||||
| D- Tx Valid Output Low | VTX-VOL | 0.3 | V | 13 | |||
| D- Rx Valid Output Low | VRX-VIL | 1 | V | 13 | |||
| Voltage Control Loop Reference | VREF | 1.21 | V | 14 | |||
| Current Control Loop Reference (SCP) | VCS+ | 60 | mV | Rsense=10mΩ, In SCP | 14 | ||
| Current Control Loop Reference (QC) | VCS+ | 36 | mV | Rsense=10mΩ, In QC | 14 |
CAD (KiCad official)
- Symbol:
JD6606SSP - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
jd6606ssp-etched.step/jd6606ssp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);jd6606ssp.step/jd6606ssp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: JADARD datasheet (18 pp, sha256
c4cc42f7b6c836a7, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).