component
IXYS IXTP15N50L2 LinearL2 N-channel MOSFET
Public Made by Adomby adom
500 V LinearL2 MOSFET, TO-220AB. Source-backed pin map and nominal CAD; mounting qualification pending.
← Commit history
Add exact-part reference page and explicitly provisional nominal library
5 files changed
+3341−3230
build_model.py+7@@ -6,6 +6,9 @@ from pathlib import Path from OCP.gp import gp_Pnt,gp_Dir,gp_Ax2 from OCP.BRepPrimAPI import BRepPrimAPI_MakeBox,BRepPrimAPI_MakeCylinder from OCP.BRepAlgoAPI import BRepAlgoAPI_Cut+from OCP.TopoDS import TopoDS_Compound+from OCP.BRep import BRep_Builder+from OCP.TopLoc import TopLoc_Location from OCP.TDocStd import TDocStd_Document from OCP.TCollection import TCollection_ExtendedString from OCP.XCAFDoc import XCAFDoc_DocumentTool,XCAFDoc_ColorType@@ -38,8 +41,12 @@ for i,name in enumerate(['Gate','Drain','Source']): parts.append((f'Lead{i+1}_Shoulder',box(x-n['b1']/2,-n['c']/2,-n['L1'],n['b1'],n['c'],n['L1']),(.7,.71,.73))) doc=TDocStd_Document(TCollection_ExtendedString('BinXCAF')) st=XCAFDoc_DocumentTool.ShapeTool_s(doc.Main());ct=XCAFDoc_DocumentTool.ColorTool_s(doc.Main())+compound=TopoDS_Compound();builder=BRep_Builder();builder.MakeCompound(compound)+assembly=st.AddShape(compound,True);TDataStd_Name.Set_s(assembly,TCollection_ExtendedString('IXTP15N50L2_AI_Nominal')) for name,shape,color in parts: label=st.AddShape(shape,False);TDataStd_Name.Set_s(label,TCollection_ExtendedString(name));ct.SetColor(label,Quantity_Color(*color,Quantity_TOC_RGB),XCAFDoc_ColorType.XCAFDoc_ColorGen)+ st.AddComponent(assembly,label,TopLoc_Location())+st.UpdateAssemblies() writer=STEPCAFControl_Writer();writer.SetColorMode(True);writer.SetNameMode(True);writer.Transfer(doc,STEPControl_AsIs) assert writer.Write(str(out/'ixtp15n50l2-ai-nominal.step'))==IFSelect_RetDone (out/'dimensions.json').write_text(json.dumps({'units':'mm','source':'IXYS DS100054B (12/11), page 2, TO-220 Outline','limits':limits,'nominalMidpoints':n,'coordinateFrame':'Z upward along straight package; body bottom Z=0; full untrimmed leads below Z=0; pin centres X=0,2.54,5.08 Y=0','limitations':['Original independent nominal envelope, not manufacturer CAD','Unspecified mold taper, edge radii and mold split omitted','Lead shoulders are simplified rectangular envelopes','No lead bend or board seating height is prescribed by this model','No manufacturer markings or internal die represented','Horizontal formed-lead footprint requires a separate pose and forming verification']},indent=2)+'\n')
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package.json+3−2@@ -16,7 +16,7 @@ "manufacturer": "IXYS / Littelfuse", "package": "TO-220AB", "pin_count": 3,- "category": "MOSFET (N-channel, linear operation)",+ "category": "Transistors", "datasheet": "https://www.littelfuse.com/~/media/electronics/datasheets/discrete_mosfets/littelfuse_discrete_mosfets_n-channel_linear_ixt_15n50_datasheet.pdf.pdf", "wiki_url": "https://wiki.adom.inc/adom/ixtp15n50l2", "parts": {@@ -85,7 +85,8 @@ "build_library.py", "ixtp15n50l2-hero.glb", "ixtp15n50l2-hero.overlay.json",- "ixtp15n50l2-board-use.glb"+ "ixtp15n50l2-board-use.glb",+ "skills/" ], "because": "No exact-MPN component record existed in two catalog searches; electronic-load project documentation is not a reusable part page.", "dependencies": {}
page.json+4−30@@ -1,6 +1,6 @@ { "slug": "ixtp15n50l2",- "type": "component",+ "type": "hardware", "kind": "component", "version": "0.1.0", "title": "IXYS IXTP15N50L2 LinearL2 N-channel MOSFET",@@ -16,7 +16,7 @@ "manufacturer": "IXYS / Littelfuse", "package": "TO-220AB", "pin_count": 3,- "category": "MOSFET (N-channel, linear operation)",+ "category": "Transistors", "datasheet": "https://www.littelfuse.com/~/media/electronics/datasheets/discrete_mosfets/littelfuse_discrete_mosfets_n-channel_linear_ixt_15n50_datasheet.pdf.pdf", "wiki_url": "https://wiki.adom.inc/adom/ixtp15n50l2", "parts": {@@ -67,31 +67,5 @@ "TO-220", "IXYS", "Littelfuse"- ],- "name": "@adom/ixtp15n50l2",- "files": [- "README.md",- "LICENSE",- "THIRD_PARTY.md",- "*.json",- "*.step",- "*.glb",- "*.kicad_sym",- "*.kicad_mod",- "*.html",- "*.png",- "datasheet.pdf",- "build_model.py",- "build_library.py",- "ixtp15n50l2-hero.glb",- "ixtp15n50l2-hero.overlay.json",- "ixtp15n50l2-board-use.glb"- ],- "because": "No exact-MPN component record existed in two catalog searches; electronic-load project documentation is not a reusable part page.",- "dependencies": {},- "org": "adom",- "author": {- "name": "John Lauer",- "email": "[email protected]"- }-}+ ]+}
skills/ixtp15n50l2/SKILL.mdadded+14@@ -0,0 +1,14 @@+---+name: ixtp15n50l2+description: Use the IXYS IXTP15N50L2 LinearL2 MOSFET catalog library, pin map and provisional nominal CAD without confusing package ratings or mounting variants with qualified electronic-load performance.+---++# IXTP15N50L2++Read README.md and provenance.json before placement. Pins are 1 Gate, 2 Drain, 3 Source; the exposed metal tab is Drain. Isolate the tab from a grounded/shared heatsink when required by the circuit. Use DS100054B's SOA curves and actual case temperature; neither 500 V, 15 A nor the 300 W case-at-25-C rating defines simultaneous load operation.++The canonical library is ixtp15n50l2.adom-lbr.json. The supplied footprint is a provisional straight-lead variant with 1.4 mm nominal finished holes at 2.54 mm pitch, not the horizontal formed-lead mounting used by an application board. Check finished-hole tolerances against the 1.02 by 0.56 mm maximum lead section (about 1.164 mm diagonal), pad clearances, assembly clearance and manufacturability. Do not use a 1.1 mm hole as a worst-case fit proof.++Original nominal CAD is reconstructed from the manufacturer drawing, not manufacturer CAD. Simplifications are explicit in dimensions.json. Body-bottom Z=0 in the source STEP; the straight-lead footprint adds an assumed 3 mm standoff. Clean board-use GLB already includes that offset; do not apply it twice. Straight leads are untrimmed and extend below the board plane. Formed/trimmed variants need separate generation, binding, native review and provenance.++Use the clean GLB for assemblies; the hero GLB includes nonphysical reference artwork. No state or thermal animation is an electrical model. Do not mark a component or board qualified from file presence, rendering success or a catalog link. Confirm dimensions, pin mapping, seating and native EDA rendering, and keep assembly/thermal qualification separate.