component

IXDI614SITR

Public Made by Adom

by adom

IXYS Pre-ordered Chips, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsixdi614sitrfactory-2.0.0extractor-text

Verified IXDI614SITR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 9 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: IXDI614SITR · SOIC-8-EP · 9 pins
  • ✓copper: 9 copper pads, none touching another net
  • ✓datasheet: all 9 pin names found in the 14-page datasheet
  • ✓distributor: lcsc C2677137, digikey 212-IXDI614SITR-ND, mouser 849-IXDI614SITR
  • ✓family: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-tho0c3tk/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.12)
  • ✓pads: 9 pins = 9 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 9 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ixdi614sitr.kicad_sym✓ ixdi614sitr.kicad_mod✓ ixdi614sitr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 10d ago
viewers ixdi614sitr: viewers · Ray 10d ago
ixdi614sitr-etched.glb Publish 0.1.0 · Ray 10d ago
ixdi614sitr-etched.step ixdi614sitr: factory component page (tier=lcsc) · Ray 10d ago
ixdi614sitr-hero.glb ixdi614sitr: hero GLB from the etched model (keeps the MPN mark) · Ray 10d ago
ixdi614sitr-hero.overlay.json Publish 0.1.0 · Ray 10d ago
ixdi614sitr.glb Publish 0.1.0 · Ray 10d ago
ixdi614sitr.kicad_mod Publish 0.1.0 · Ray 10d ago
ixdi614sitr.kicad_sym Publish 0.1.0 · Ray 10d ago
ixdi614sitr.lbr Publish 0.1.0 · Ray 10d ago
ixdi614sitr.step Publish 0.1.0 · Ray 10d ago
package.json Publish 0.1.0 · Ray 10d ago
page.json Set visibility: public · Ray 10d ago
README.md Publish 0.1.0 · Ray 10d ago
verification.json Verified: Published by the parts factory: tier lcsc, 9 pins · Ray 10d ago

IXDI614SITR

IXYS · Pre-ordered Chips · SOIC-8-EP

IXDI614SITR from IXYS, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Supply voltage pin that powers the device, recommended 4.5V to 35V (absolute maximum 40V).
2 IN input Logic input of the inverting driver (IXDI614); VIH min 3.0V and VIL max 0.8V at 25°C, and it withstands a negative swing down to -5V.
3 NC unconnected Not connected.
4 GND power_in Ground, the common ground reference for the device.
5 GND power_in Ground, the common ground reference for the device.
6 OUT output Inverted output that sources or sinks up to 14A peak current to turn a discrete MOSFET or IGBT on or off.
7 OUT output Inverted output that sources or sinks up to 14A peak current to turn a discrete MOSFET or IGBT on or off.
8 VCC power_in Supply voltage pin that powers the device, recommended 4.5V to 35V (absolute maximum 40V).
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer IXYS
Package SOIC-8-EP
Category Interface ICs
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage, Low VIL 0.8 V TA=25°C; 4.5V < VCC < 18V 4
Input Voltage, High VIH 3 V TA=25°C; 4.5V < VCC < 18V 4
Input Current IIN -10 10 µA TA=25°C; 0V < VIN < VCC 4
Output Voltage, Low VOL 0.025 V TA=25°C 4
Output Resistance, High State ROH 0.4 0.8 Ω TA=25°C; VCC=18V, IOUT=-100mA 4
Output Resistance, Low State ROL 0.3 0.6 Ω TA=25°C; VCC=18V, IOUT=100mA 4
Output Current, Continuous IDC -4 4 A TA=25°C; Limited by package power dissipation 4
Rise Time tR 25 35 ns TA=25°C; CLOAD=15nF, VCC=18V 4
Fall Time tF 18 25 ns TA=25°C; CLOAD=15nF, VCC=18V 4
On-Time Propagation Delay tONDELAY 50 70 ns TA=25°C; CLOAD=15nF, VCC=18V 4
Off-Time Propagation Delay tOFFDELAY 50 70 ns TA=25°C; CLOAD=15nF, VCC=18V 4
Power Supply Current ICC 1 2 mA TA=25°C; VCC=18V, VIN=3.5V 4
Power Supply Current ICC 10 µA TA=25°C; VCC=18V, VIN=0V 4
Input Voltage, High VIH 3.3 V TA=-40°C to +125°C; 4.5V < VCC < 18V 5
Input Voltage, Low VIL 0.65 V TA=-40°C to +125°C; 4.5V < VCC < 18V 5
Input Current IIN -10 10 µA TA=-40°C to +125°C; 0V < VIN < VCC 5
Output Voltage, Low VOL 0.025 V TA=-40°C to +125°C 5
Output Resistance, High State ROH 1.5 Ω TA=-40°C to +125°C; VCC=18V, IOUT=-100mA 5
Output Resistance, Low State ROL 1.2 Ω TA=-40°C to +125°C; VCC=18V, IOUT=100mA 5
Output Current, Continuous IDC -1 1 A TA=-40°C to +125°C; Limited by package power dissipation 5
Rise Time tR 50 ns TA=-40°C to +125°C; CLOAD=15nF, VCC=18V 5
Fall Time tF 40 ns TA=-40°C to +125°C; CLOAD=15nF, VCC=18V 5
On-Time Propagation Delay tONDELAY 90 ns TA=-40°C to +125°C; CLOAD=15nF, VCC=18V 5
Off-Time Propagation Delay tOFFDELAY 90 ns TA=-40°C to +125°C; CLOAD=15nF, VCC=18V 5
Power Supply Current ICC 3 mA TA=-40°C to +125°C; VCC=18V, VIN=3.5V 5
Power Supply Current ICC 150 µA TA=-40°C to +125°C; VCC=18V, VIN=0V 5
Supply Voltage VCC -0.3 40 V 3
Input Voltage VIN, VEN -5 V 3
Output Current IOUT -14 14 A 3
Junction Temperature TJ -55 150 °C 3
Storage Temperature TSTG -65 150 °C 3
Supply Voltage VCC 4.5 35 V 3
Operating Temperature Range TA -40 125 °C 3
Thermal Impedance, Junction-to-Ambient (SI, 8-Pin Power SOIC) JA 85 °C/W 6
Thermal Impedance, Junction-to-Case (SI, 8-Pin Power SOIC) JC 10 °C/W 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC Circuits Division classifies its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of prod 11

CAD (KiCad official)

  • Symbol: IXDI614SITR
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: ixdi614sitr-etched.step / ixdi614sitr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ixdi614sitr.step / ixdi614sitr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: IXYS datasheet (14 pp, sha256 d958e4f5eb8be9b4, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF