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IX4340NETR
Public Made by Adomby adom
Littelfuse IXYS Gate Drivers, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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IX4340NETR
Littelfuse IXYS · Gate Drivers · SOIC-8-EP
IX4340NETR from Littelfuse IXYS, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ENA | input | Enable input for Channel A; a logic high (or floating) enables Channel A, and a logic low disables OUTA and holds it low regardless of INA. |
| 2 | INA | input | Channel A logic input, internally pulled to GND, with VIL maximum 0.8V and VIH minimum 2.5V at VCC=12V. |
| 3 | GND | power_in | Ground, the common ground reference for the device; the thermal pad may be connected to GND or left floating. |
| 4 | INB | input | Channel B logic input, internally pulled to GND, with VIL maximum 0.8V and VIH minimum 2.5V at VCC=12V. |
| 5 | OUTB | output | Channel B output, capable of sourcing and sinking 5A. |
| 6 | VCC | power_in | Supply voltage, specified for 5V to 20V operation with an absolute maximum rating of -0.3V to 20V. |
| 7 | OUTA | output | Channel A output, capable of sourcing and sinking 5A. |
| 8 | ENB | input | Enable input for Channel B; a logic high (or floating) enables Channel B, and a logic low disables OUTB and holds it low regardless of INB. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Littelfuse IXYS |
| Package | SOIC-8-EP |
| Category | Motor Driver ICs |
| Pins | 9 |
CAD (KiCad official)
- Symbol:
IX4340NETR - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
ix4340netr-etched.step/ix4340netr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ix4340netr.step/ix4340netr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Littelfuse IXYS datasheet (10 pp, sha256
9a5e411c9a83d716, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# IX4340NETR
**Littelfuse IXYS** · Gate Drivers · SOIC-8-EP
IX4340NETR from Littelfuse IXYS, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ENA | input | Enable input for Channel A; a logic high (or floating) enables Channel A, and a logic low disables OUTA and holds it low regardless of INA. |
| 2 | INA | input | Channel A logic input, internally pulled to GND, with VIL maximum 0.8V and VIH minimum 2.5V at VCC=12V. |
| 3 | GND | power_in | Ground, the common ground reference for the device; the thermal pad may be connected to GND or left floating. |
| 4 | INB | input | Channel B logic input, internally pulled to GND, with VIL maximum 0.8V and VIH minimum 2.5V at VCC=12V. |
| 5 | OUTB | output | Channel B output, capable of sourcing and sinking 5A. |
| 6 | VCC | power_in | Supply voltage, specified for 5V to 20V operation with an absolute maximum rating of -0.3V to 20V. |
| 7 | OUTA | output | Channel A output, capable of sourcing and sinking 5A. |
| 8 | ENB | input | Enable input for Channel B; a logic high (or floating) enables Channel B, and a logic low disables OUTB and holds it low regardless of INB. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Littelfuse IXYS |
| Package | SOIC-8-EP |
| Category | Motor Driver ICs |
| Pins | 9 |
## CAD (KiCad official)
- Symbol: `IX4340NETR`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files: `ix4340netr-etched.step` / `ix4340netr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ix4340netr.step` / `ix4340netr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Littelfuse IXYS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589041987215769600) (10 pp, sha256 `9a5e411c9a83d716`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ix4340netr-datasheet.pdf)