# IW1799-02

**Dialog Semiconductor** · AC-DC Controllers & Regulators · SOIC-8

IW1799-02 from Dialog Semiconductor, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSENSE | input | Auxiliary voltage sense input used for primary-side regulation, rated -0.7 to 10.0 V with IVsense ≤ 10 mA. |
| 2 | DLNK | output | Digital communication link for secondary-to-primary rapid charge information (voltage requests, current limits, undershoot and over-voltage), rated -0.7 to 5.0 V. |
| 3 | SD | input | External shutdown control input, which can also be configured for external over-temperature protection by connecting an NTC resistor to ground, rated -0.7 to 5.0 V. |
| 4 | VCC | power_in | IC power supply pin, rated -0.3 to 45.0 V with a continuous DC supply current of 20 mA max. |
| 5 | GND | power_in | Ground reference for the device. |
| 6 | GATE | output | Gate drive output for the external MOSFET switch, rated -0.3 to 30 V. |
| 7 | CS/CDC | input | Primary-side current sense input for cycle-by-cycle peak-current control and limit, and used during configuration to set the CDC compensation level, rated -0.7 to 5.0 V. |
| 8 | DET | input | Input for external VIN OVP protection or X-cap discharge function, rated -0.7 to 5.0 V; OVP triggers when DET is above 0.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Dialog Semiconductor |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage range | VCC | -0.3 |  | 45 | V | pin 4, ICC = 20mA max | 4 |
| Continuous DC supply current at VCC pin | ICC |  |  | 20 | mA | VCC = 15V | 4 |
| VSENSE input |  | -0.7 |  | 10 | V | pin 1, IVsense ≤ 10mA | 4 |
| DLNK pin voltage |  | -0.7 |  | 5 | V | pin 2 | 4 |
| CS/CDC pin voltage |  | -0.7 |  | 5 | V | pin 7 | 4 |
| SD pin voltage |  | -0.7 |  | 5 | V | pin 3 | 4 |
| GATE pin voltage |  | -0.3 |  | 30 | V | pin 6 | 4 |
| DET pin voltage |  | -0.7 |  | 5 | V | pin 8 | 4 |
| Maximum junction temperature | TJMAX |  |  | 150 | °C |  | 4 |
| Operating junction temperature | TJOPT | -40 |  | 150 | °C |  | 4 |
| Storage temperature | TSTG | -65 |  | 150 | °C |  | 4 |
| Thermal resistance junction-to-ambient | θJA |  |  | 160 | °C/W |  | 4 |
| ESD rating |  | -2000 |  | 2000 | V | per JEDEC JESD22-A114 | 4 |
| Latch-up test |  | -100 |  | 100 | mA | per JESD78D | 4 |
| Maximum operating VCC voltage |  |  |  | 40 | V | at 21V output (design consideration, Section 9.17) | 17 |
| VCC start-up threshold | VCC(ST) |  |  | 21.5 | V | VCC rising | 5 |
| VCC under-voltage lockout threshold | VCC(UVL) |  |  | 8.2 | V | VCC falling | 5 |
| VCC latch release threshold | VCC(RLS) |  |  | 7 | V | VCC falling | 5 |
| VCC over-voltage protection level | VCC(OVP) |  |  | 42 | V | VCC rising | 5 |
| Start-up current | IIN(ST) |  |  | 7 | μA | VCC = 16V | 5 |
| Quiescent current | ICCQ |  |  | 2.5 | mA | VCC = 20V, excluding gate driver switching current | 5 |
| No-load operating current | ICC_NL |  |  | 0.22 | mA | No-load operation | 5 |
| Nominal voltage at 5V output | VSENSE_5V(NOM) |  |  | 0.93 | V | 5V VOUT, TA = 25°C, negative edge | 5 |
| Output OVP threshold with no CDC compensation at 5V output | VSENSE_5V(MAX) |  |  | 1.116 | V | 5V VOUT, TA = 25°C, negative edge | 5 |
| DLNK detection threshold (falling edge) | VDLNK-TH(F) |  |  | 1.6 | V |  | 5 |
| DLNK recovery threshold (rising edge) | VDLNK-TH(R) |  |  | 1.8 | V |  | 5 |
| DLNK current source | IDLNK |  |  | 500 | μA |  | 5 |
| Switching-cycle over-current threshold | VOCP |  |  | 0.92 | V |  | 5 |
| CS regulation upper limit | VIPK(HIGH) |  |  | 0.8 | V |  | 5 |
| CS regulation lower limit | VIPK(LOW) |  |  | 0.184 | V |  | 5 |
| Configuration current source | ICFG |  |  | 500 | μA |  | 5 |
| Driver pull-down ON-resistance | RDS(ON)PD |  |  | 12 | Ω | ISINK = 5mA | 6 |
| Driver pull-up ON-resistance | RDS(ON)PU |  |  | 99 | Ω | ISOURCE = 5mA | 6 |
| GATE rise time | tR |  |  | 95 | ns | TA = 25°C, CL = 330pF, 10% to 90% | 6 |
| GATE fall time | tF |  |  | 14 | ns | TA = 25°C, CL = 330pF, 90% to 10% | 6 |
| Maximum GATE pin voltage at switching mode | VGATE(MAX) |  |  | 10.3 | V | TA = 25°C | 6 |
| Maximum switching frequency at < 8V VOUT | fSW_LV_PWM |  |  | 76 | kHz | At PWM mode | 6 |
| Maximum switching frequency at ≥ 8V VOUT | fSW_HV_PWM |  |  | 86 | kHz | At PWM mode | 6 |
| Shutdown threshold (falling edge) | VSD-TH(F) |  |  | 1 | V |  | 6 |
| Shutdown threshold before start-up | VSD-TH(ST_F) |  |  | 1.2 | V |  | 6 |
| Shutdown current source | ISD |  |  | 100 | μA |  | 6 |
| OVP detection threshold | VOVP_TH |  |  | 0.5 | V |  | 6 |
| Thermal shutdown threshold | TSD |  |  | 140 | °C |  | 6 |
| Thermal shutdown recovery | TSD-R |  |  | 130 | °C |  | 6 |

## CAD (KiCad official)

- Symbol: `IW1799-02`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `iw1799-02-etched.step` / `iw1799-02-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `iw1799-02.step` / `iw1799-02.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Dialog Semiconductor datasheet](docs/iw1799-02-datasheet.pdf) (20 pp, sha256 `712f5e66d5ed90fd`, retrieved 2026-10-30, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/iw1799-02-datasheet.pdf)