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ISPPAC-POWR605-01SN24I

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Lattice Monitors & Reset Circuits, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsisppac-powr605-01sn24ifactory-2.0.0extractor-text

Verified ISPPAC-POWR605-01SN24I

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 25 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ISPPAC-POWR605-01SN24I · QFN-24-EP(4x4) · 25 pins
  • ✓copper: 25 copper pads, none touching another net
  • ✓datasheet: all 25 pin names found in the 30-page datasheet
  • ✓distributor: lcsc C1529894, digikey 220-1359-ND, mouser 842-POWR605-01SN241
  • ✓family: QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-cviiqhl7/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 25 pins = 25 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 25 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ isppac-powr605-01sn24i.kicad_sym✓ isppac-powr605-01sn24i.kicad_mod✓ isppac-powr605-01sn24i.step
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Ray Publish 0.1.0 40c968d 8d ago

ISPPAC-POWR605-01SN24I

Lattice · Monitors & Reset Circuits · QFN-24-EP(4x4)

ISPPAC-POWR605-01SN24I from Lattice, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VMON1 passive Analog voltage monitor input rated -0.3 V to 5.9 V, which can be biased independently from VCC.
2 VMON2 passive Analog voltage monitor input rated -0.3 V to 5.9 V, which can be biased independently from VCC.
3 VCC power_in Core supply pin, 2.64 V to 3.96 V; both VCC pins must be connected together on the circuit board.
4 VMON3 passive Analog voltage monitor input rated -0.3 V to 5.9 V; connect to the 3.3 V rail if unused.
5 VMON4 passive Analog voltage monitor input rated -0.3 V to 5.9 V; connect to the 3.3 V rail if unused.
6 VMON5 passive Analog voltage monitor input rated -0.3 V to 5.9 V; connect to the 3.3 V rail if unused.
7 VMON6 passive Analog voltage monitor input rated -0.3 V to 5.9 V; connect to the 3.3 V rail if unused.
8 GND power_in Ground reference; all GND pins must be connected together on the circuit board.
9 GND power_in Ground reference; all GND pins must be connected together on the circuit board.
10 VCCJ power_in JTAG logic supply rated 2.25 V to 3.6 V; leave open during power-down mode because a connected supply draws about 2.2 mA then.
11 TDO output JTAG test data output, 0 V to 5.5 V.
12 TCK input JTAG test clock input, 0 V to 5.5 V.
13 TDI input JTAG test data input, 0 V to 5.5 V, with internal pull-up.
14 TMS input JTAG test mode select input, 0 V to 5.5 V, with internal pull-up.
15 IN_OUT5 bidirectional Digital I/O configurable as PLD input (0 V to 5.5 V, thresholds referenced to VCC) or as open-drain output requiring an external pull-up to a supply.
16 VCC power_in Core supply pin, 2.64 V to 3.96 V; both VCC pins must be connected together on the circuit board.
17 IN_OUT4 bidirectional Digital I/O configurable as PLD input (0 V to 5.5 V, thresholds referenced to VCC) or as open-drain output requiring an external pull-up to a supply.
18 IN_OUT3 bidirectional Digital I/O configurable as PLD input (0 V to 5.5 V, thresholds referenced to VCC) or as open-drain output requiring an external pull-up to a supply.
19 IN_OUT2 bidirectional Digital I/O configurable as PLD input (0 V to 5.5 V, thresholds referenced to VCC) or as open-drain output requiring an external pull-up to a supply.
20 IN_OUT1 bidirectional Digital I/O configurable as PLD input (0 V to 5.5 V, thresholds referenced to VCC) or as open-drain output requiring an external pull-up to a supply.
21 IN2 input PLD logic input 2 rated 0 V to 5.5 V; tie to GND when not used.
22 IN1_PWRDN input PLD logic input 1 rated 0 V to 5.5 V, usable as the power-down input (low enters, high exits) and to be pulled down with 10 kΩ when not used.
23 NC unconnected No internal connection.
24 NC unconnected No internal connection.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Lattice
Package QFN-24-EP(4x4)
Category Power Management ICs
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Core supply voltage at pin VCC 2.64 3.96 V 4
JTAG logic supply voltage at pin VCCJ 2.25 3.6 V 4
Input voltage at digital input pins VIN -0.3 5.5 V 4
Input voltage at VMON pins VMON -0.3 5.9 V 4
Open-drain output voltage IN_OUT[1:5] pins VOUT -0.3 5.5 V 4
Ambient temperature during programming (Note 1) TAPROG -40 85 °C 4
Ambient temperature TA -40 105 °C Power applied 4
Operating junction temperature TJOP -40 108 °C Power applied 4
Core supply VCC -0.5 4.5 V 4
JTAG logic supply VCCJ -0.5 6 V 4
Digital input voltage (all digital I/O pins) VIN -0.5 6 V 4
VMON input voltage VMON -0.5 6 V 4
Voltage applied to tri-stated pins IN_OUT[1:5] VTRI -0.5 6 V 4
Storage temperature TS -65 150 °C 4
Ambient temperature TA -65 125 °C 4
Maximum sink current on any output ISINKMAX 23 mA 4
Supply current ICC1 3.5 5 mA Includes currents on both VCC pins 4
Power-down mode supply current ICC_PWRDN 10 µA ICC + pin leakage currents 4
Input resistance RIN 55 65 75 k 5
Programmable trip-point range VMON Range 0.075 5.793 V 5
Near-ground sense threshold VZ 70 75 80 mV 5
Absolute accuracy of any trip-point VMON Accuracy 0.7 % 25 °C, trip point <2.7 V 5
Absolute accuracy of any trip-point VMON Accuracy 0.8 % 25 °C, trip point >2.7 V 5
Minimum duration brown out required to enter reset state TBRO 1 5 µs 6
Supply frequency MCLK timing fMCLK 7.6 8 8.4 MHz MCLK timing 7
PLDCLK frequency fPLDCLK 250 kHz PLDCLK frequency = MCLK 32 7
Timeout Range 0.032 1966 ms Range of programmable timers (128 steps) 7
Timer accuracy -12.5 -6.67 % fMCLK = 8.0 MHz 7
Minimum required time in power-down mode before power-up can occur TPWRDN_HOLD 100 µs 7
Program enable delay time tISPEN 10 µs 9
Program disable delay time tISPDIS 30 µs 9
High voltage discharge time, program tHVDIS 30 µs 9
High voltage discharge time, erase tHVDIS 200 µs 9
Falling edge of TCK to TDO active tCEN 10 ns 9
Falling edge of TCK to TDO disable tCDIS 10 ns 9
Setup time tSU1 5 ns 9
Hold time tH 10 ns 9
TCK clock pulse width, high tCKH 20 ns 9
TCK clock pulse width, low tCKL 20 ns 9
Maximum TCK clock frequency fMAX 25 MHz 9
Falling edge of TCK to valid output tCO 10 ns 9
Verify pulse width tPWV 30 µs 9
Programming pulse width tPWP 20 ms 9
Input leakage, no pull-up/pull-down IIL,IIH -10 10 µA no pull-up/pull-down 8
Voltage input, logic low VIL 0.8 V TDI, TMS, TCK, IN[1:2], IN_OUT[1:5], VCCJ = 3.3 V supply 8
Voltage input, logic low VIL 0.7 V TDI, TMS, TCK, VCCJ = 2.5 V supply 8
Voltage input, logic high VIH 2 V TDI, TMS, TCK, IN[1:2], IN_OUT[1:5], VCCJ = 3.3 V supply 8
Voltage input, logic high VIH 1.7 V TDI, TMS, TCK, VCCJ = 2.5 V supply 8
Digital output low voltage IN_OUT[1:5] VOL 0.8 V ISINK = 20 mA 8
Digital output low voltage TDO VOL 0.4 V ISINK = 4 mA 8
Output sink current per digital output IN_OUT[1:5] ISINK 20 mA VOL < 0.8 V 8
Sum of maximum current sink from all digital outputs ISINKTOTAL 67 mA All digital outputs 8
Leakage (parameter name blank in table) 1 µA Chip powered down, outputs pulled up to 3.6 V 8
Input capacitance CIN 8 pF 5
Supply current ICCJ 1 mA 4
Power-on reset: threshold below which POR is LOW VTL 2.2 V Corresponds to VCC supply voltage 6
Power-on reset: threshold above which POR is HIGH VTH 2.5 V Corresponds to VCC supply voltage 6
Power-on reset: threshold above which POR is valid VT 0.8 V Corresponds to VCC supply voltage 6
Input pull-up current (TMS, TDI) IPU 70 µA 8
Threshold temperature coefficient TEMPCO_THRESHOLD 60 ppm/c 5

CAD (KiCad official)

  • Symbol: ISPPAC-POWR605-01SN24I
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: isppac-powr605-01sn24i-etched.step / isppac-powr605-01sn24i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isppac-powr605-01sn24i.step / isppac-powr605-01sn24i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Lattice datasheet (30 pp, sha256 82ec9d299e6c29fe, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF