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ISPPAC-POWR1014-01TN48I

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Lattice Monitors & Reset Circuits, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsisppac-powr1014-01tn48ifactory-2.0.0extractor-text

Verified ISPPAC-POWR1014-01TN48I

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ISPPAC-POWR1014-01TN48I · TQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 53-page datasheet
  • ✓distributor: lcsc C1519381, digikey 220-1266-ND, mouser 842-CPOWR101401TN48I
  • ✓family: TQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-1vij0t4b/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ isppac-powr1014-01tn48i.kicad_sym✓ isppac-powr1014-01tn48i.kicad_mod✓ isppac-powr1014-01tn48i.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers isppac-powr1014-01tn48i: viewers · Ray 8d ago
isppac-powr1014-01tn48i-etched.glb Publish 0.1.0 · Ray 8d ago
isppac-powr1014-01tn48i-etched.step isppac-powr1014-01tn48i: factory component page (tier=lcsc) · Ray 8d ago
isppac-powr1014-01tn48i-hero.glb isppac-powr1014-01tn48i: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
isppac-powr1014-01tn48i-hero.overlay.json Publish 0.1.0 · Ray 8d ago
isppac-powr1014-01tn48i.glb Publish 0.1.0 · Ray 8d ago
isppac-powr1014-01tn48i.kicad_mod Publish 0.1.0 · Ray 8d ago
isppac-powr1014-01tn48i.kicad_sym Publish 0.1.0 · Ray 8d ago
isppac-powr1014-01tn48i.lbr Publish 0.1.0 · Ray 8d ago
isppac-powr1014-01tn48i.step Publish 0.1.0 · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago
verification.json Verified: Published by the parts factory: tier lcsc, 48 pins · Ray 8d ago

ISPPAC-POWR1014-01TN48I

Lattice · Monitors & Reset Circuits · TQFP-48(7x7)

ISPPAC-POWR1014-01TN48I from Lattice, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT14 output Open-drain digital output 14, 0 V to 5.5 V; requires an external pull-up resistor to a supply.
2 OUT13 output Open-drain digital output 13, 0 V to 5.5 V; requires an external pull-up resistor to a supply.
3 OUT12 output Open-drain digital output 12, 0 V to 5.5 V; requires an external pull-up resistor to a supply.
4 OUT11 output Open-drain digital output 11, 0 V to 5.5 V; requires an external pull-up resistor to a supply.
5 OUT10 output Open-drain digital output 10, 0 V to 5.5 V; requires an external pull-up resistor to a supply.
6 OUT9 output Open-drain digital output 9, 0 V to 5.5 V; requires an external pull-up resistor to a supply.
7 GNDD power_in Digital ground; must be connected to GNDA on the circuit board.
8 OUT8 output Open-drain digital output 8, 0 V to 5.5 V; requires an external pull-up resistor to a supply.
9 OUT7 output Open-drain digital output 7, 0 V to 5.5 V; requires an external pull-up resistor to a supply.
10 OUT6 output Open-drain digital output 6, 0 V to 5.5 V; requires an external pull-up resistor to a supply.
11 OUT5 output Open-drain digital output 5, 0 V to 5.5 V; requires an external pull-up resistor to a supply.
12 OUT4 output Open-drain digital output 4, 0 V to 5.5 V; requires an external pull-up resistor to a supply.
13 SMBA_OUT3 output Open-drain digital output 3, 0 V to 5.5 V; the SMBUS alert function on this pin is available only on the ispPAC-POWR1014A.
14 HVOUT2 output Open-drain or high-voltage FET gate driver output 2, 0 V to 13 V in open-drain mode; in FET mode it sources 12.5 µA to 100 µA and sinks 100 µA to 3000 µA.
15 HVOUT1 output Open-drain or high-voltage FET gate driver output 1, 0 V to 13 V in open-drain mode; in FET mode it sources 12.5 µA to 100 µA and sinks 100 µA to 3000 µA.
16 TMS input JTAG test mode select input, 0 V to 5.5 V; internally pulled up.
17 ATDI input Alternate JTAG test data input, used when TDISEL = 0, 0 V to 5.5 V; internally pulled up.
18 TDI input JTAG test data input, used when TDISEL = 1, 0 V to 5.5 V; internally pulled up.
19 TDISEL input Selects TDI (TDISEL = 1) or ATDI (TDISEL = 0) as the JTAG data input, 0 V to 5.5 V; internally pulled up.
20 VCCJ power_in JTAG logic interface supply, 2.25 V to 3.6 V.
21 TDO output JTAG test data output, 0 V to 5.5 V.
22 TCK input JTAG test clock input, 0 V to 5.5 V.
23 VCCD power_in Core supply, 2.8 V to 3.96 V; must be connected to VCCA on the circuit board.
24 APS power_in Alternate E2 programming supply, 3.0 V to 3.6 V, used only when VCCD and VCCA are not powered; must be left floating when VCCD and VCCA are powered.
25 VMON1 passive Voltage monitor 1 analog input, -0.3 V to 5.87 V; unused VMON inputs should be tied to GND.
26 VMON2 passive Voltage monitor 2 analog input, -0.3 V to 5.87 V; unused VMON inputs should be tied to GND.
27 VMON3 passive Voltage monitor 3 analog input, -0.3 V to 5.87 V; unused VMON inputs should be tied to GND.
28 VMON4 passive Voltage monitor 4 analog input, -0.3 V to 5.87 V; unused VMON inputs should be tied to GND.
29 VCCA power_in Analog power supply, 2.8 V to 3.96 V.
30 GNDA power_in Analog ground; must be connected to GNDD on the circuit board.
31 GNDD power_in Digital ground; must be connected to GNDA on the circuit board.
32 VMON5 passive Voltage monitor 5 analog input, -0.3 V to 5.87 V; unused VMON inputs should be tied to GND.
33 VMON6 passive Voltage monitor 6 analog input, -0.3 V to 5.87 V; unused VMON inputs should be tied to GND.
34 VMON7 passive Voltage monitor 7 analog input, -0.3 V to 5.87 V; unused VMON inputs should be tied to GND.
35 VMON8 passive Voltage monitor 8 analog input, -0.3 V to 5.87 V; unused VMON inputs should be tied to GND.
36 VMON9 passive Voltage monitor 9 analog input, -0.3 V to 5.87 V; unused VMON inputs should be tied to GND.
37 VMON10 passive Voltage monitor 10 analog input, -0.3 V to 5.87 V; unused VMON inputs should be tied to GND.
38 GNDD power_in Printed as SDA on the ispPAC-POWR1014A; on the ispPAC-POWR1014 (this part) it must be connected to GNDD.
39 GNDD power_in Printed as SCL on the ispPAC-POWR1014A; on the ispPAC-POWR1014 (this part) it must be connected to GNDD.
40 RESETb bidirectional Active-low device reset, 0 V to 3.96 V; internally pulled up and should be left open unless cascading two or more devices.
41 VCCD power_in Core supply, 2.8 V to 3.96 V; must be connected to VCCA on the circuit board.
42 PLDCLK output 250 kHz PLD clock output, CMOS, 0 V to 3.96 V, tristate; internally pulled up.
43 MCLK bidirectional 8 MHz clock I/O, CMOS drive, 0 V to 3.96 V; tristated in standalone mode, outputs the clock in master mode and is an input in slave mode.
44 IN1 input PLD logic input 1, registered by MCLK; threshold referenced to VCCINP, and unused INx inputs should be tied to GNDD.
45 VCCINP power_in Supply for the IN[1:4] input thresholds, 2.25 V to 5.5 V.
46 IN2 input PLD logic input 2, registered by MCLK; threshold referenced to VCCINP, and unused INx inputs should be tied to GNDD.
47 IN3 input PLD logic input 3, registered by MCLK; threshold referenced to VCCINP, and unused INx inputs should be tied to GNDD.
48 IN4 input PLD logic input 4, registered by MCLK; threshold referenced to VCCINP, and unused INx inputs should be tied to GNDD.

Key specifications

Parameter Value
Manufacturer Lattice
Package TQFP-48(7x7)
Category Power Management ICs
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Core supply VCCD -0.5 4.5 V 5
Analog supply VCCA -0.5 4.5 V 5
Digital input supply (IN[1:4]) VCCINP -0.5 6 V 5
JTAG logic supply VCCJ -0.5 6 V 5
Alternate E2 programming supply APS -0.5 4 V 5
Digital input voltage (all digital I/O pins) VIN -0.5 6 V 5
VMON input voltage VMON -0.5 6 V 5
Voltage applied to tri-stated pins VTRI -0.5 13.3 V HVOUT[1:2] 5
Voltage applied to tri-stated pins VTRI -0.5 6 V OUT[3:14] 5
Maximum sink current on any output ISINKMAXTOTAL 23 mA 5
Storage temperature TS -65 150 °C 5
Ambient temperature TA -65 125 °C 5
Core supply voltage at pin VCCD, VCCA 2.8 3.96 V 5
Digital input supply for IN[1:4] at pin VCCINP 2.25 5.5 V 5
JTAG logic supply voltage at pin VCCJ 2.25 3.6 V 5
Alternate E2 programming supply at pin APS 3 3.6 V VCCD and VCCA not powered 5
Input voltage at digital input pins VIN -0.3 5.5 V 5
Input voltage at VMON pins VMON -0.3 5.9 V 5
Open-drain output voltage VOUT -0.3 5.5 V OUT[3:14] pins 5
Open-drain output voltage VOUT -0.3 13 V HVOUT[1:2] pins in open-drain mode 5
Ambient temperature during programming TAPROG -40 85 °C 5
Ambient temperature TA -40 85 °C Power applied 5
Supply current ICC1 20 mA 6
Supply current ICCINP 5 mA 6
Supply current ICCJ 1 mA 6
Input resistance RIN 55 65 75 k 6
Programmable trip-point range VMON Range 0.075 5.867 V 6
Near-ground sense threshold VZ 70 75 80 mV 6
Absolute accuracy of any trip-point VMON Accuracy 0.3 0.9 % 6
Gate driver output voltage VPP 9.6 10 10.4 V 10 V setting 6
Gate driver output voltage VPP 7.7 8 8.3 V 8 V setting 6
Gate driver output voltage VPP 5.8 6 6.2 V 6 V setting 6
Gate driver sink current (LOW state) IOUTSINK 2000 3000 µA FAST OFF mode 6
Delay from RESETb HIGH to PLDCLK rising edge TSTART 5 10 µs 7
Minimum duration brown out required to trigger RESETb TBRO 1 5 µs 7
Capacitive load on RESETb for master/slave operation CL 200 pF 7
Internal master clock frequency (MCLK) fCLK 7.6 8 8.4 MHz 9
Externally applied master clock (MCLK) fCLKEXT 7.2 8.8 MHz 9
Range of programmable timers (128 steps) Timeout Range 0.032 1966 ms Range of programmable timers (128 steps), fCLK = 8MHz 9
Timer accuracy Accuracy -12.5 -6.67 % fCLK = 8MHz 9
Input leakage IIL,IIH -10 10 µA no pull-up/pull-down 10
Output leakage current IOH-HVOUT 35 60 µA HVOUT[1:2] in open drain mode and pulled up to 10 V 10
Output leakage current IOH-HVOUT 35 100 µA HVOUT[1:2] in open drain mode and pulled up to 13 V 10
Voltage input, logic low VIL 0.8 V TDI, TMS, ATDI, TDISEL, 3.3 V supply 10
Voltage input, logic low VIL 0.7 V TDI, TMS, ATDI, TDISEL, 2.5 V supply 10
Voltage input, logic high VIH 2 V TDI, TMS, ATDI, TDISEL, 3.3 V supply 10
Voltage input, logic high VIH 1.7 V TDI, TMS, ATDI, TDISEL, 2.5 V supply 10
Voltage output, logic low VOL 0.8 V HVOUT[1:2] (open drain mode), ISINK = 10 mA 10
Voltage output, logic low VOL 0.4 V TDO, MCLK, PLDCLK, SDA ISINK = 4 mA 10
All digital outputs total sink current ISINKTOTAL 67 mA All digital outputs 10
Program enable delay time tISPEN 10 µs 12
Program disable delay time tISPDIS 30 µs 12
High voltage discharge time tHVDIS 30 µs program 12
High voltage discharge time tHVDIS 200 µs erase 12
Setup time tSU1 5 ns 12
Hold time tH 10 ns 12
Maximum TCK clock frequency fMAX 25 MHz 12
Programming pulse width tPWP 20 ms 12

CAD (KiCad official)

  • Symbol: ISPPAC-POWR1014-01TN48I
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: isppac-powr1014-01tn48i-etched.step / isppac-powr1014-01tn48i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isppac-powr1014-01tn48i.step / isppac-powr1014-01tn48i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Lattice datasheet (53 pp, sha256 62184ff40e285d2e, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF