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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ISOW7844FDWER

Texas Instruments · Digital Isolators (With Power) · SOIC-16-300mil

ISOW7844FDWER from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC	power_in	Power supply voltage input ranging from 3V to 5.5V, powers primary-side control circuits and signal isolation channels.
2	GND1	power_in	Ground reference for VCC power supply side.
3	OUTA	output	Output channel A, single-ended CMOS/LVCMOS logic output representing isolated signal state, sources 4 mA at 5V or 2 mA at 3.3V per section 7.3.
4	OUTB	output	Output channel B, single-ended CMOS/LVCMOS logic output representing isolated signal state, sources 4 mA at 5V or 2 mA at 3.3V per section 7.3.
5	OUTC	output	Output channel C, single-ended CMOS/LVCMOS logic output representing isolated signal state, sources 4 mA at 5V or 2 mA at 3.3V per section 7.3.
6	OUTD	output	Output channel D, single-ended CMOS/LVCMOS logic output representing isolated signal state, sources 4 mA at 5V or 2 mA at 3.3V per section 7.3.
7	NC	unconnected	No connection.
8	GND1	power_in	Ground reference for VCC power supply side.
9	GND2	power_in	Ground reference for VISO isolated power supply side.
10	SEL	input	VISO voltage selection input; tie to VISO for 5V output or to GND2 or leave floating for 3.3V output per section 9.4.
11	IND	input	Input channel D, single-ended CMOS/LVCMOS logic input with VIH threshold of 0.7×VSI and VIL threshold of 0.3×VSI per section 7.3.
12	INC	input	Input channel C, single-ended CMOS/LVCMOS logic input with VIH threshold of 0.7×VSI and VIL threshold of 0.3×VSI per section 7.3.
13	INB	input	Input channel B, single-ended CMOS/LVCMOS logic input with VIH threshold of 0.7×VSI and VIL threshold of 0.3×VSI per section 7.3.
14	INA	input	Input channel A, single-ended CMOS/LVCMOS logic input with VIH threshold of 0.7×VSI and VIL threshold of 0.3×VSI per section 7.3.
15	GND2	power_in	Ground reference for VISO isolated power supply side.
16	VISO	power_out	Isolated supply output voltage, selectable as 3.3V or 5V via SEL pin, sources up to 130 mA at 5V or 75 mA at 3.3V per section 7.3.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16-300mil
Category	Signal Isolation Devices
Pins	16

CAD (KiCad official)

Symbol: ISOW7844FDWER
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16-300mil (KiCad packages3D, STEP)
3D model files: isow7844fdwer-etched.step / isow7844fdwer-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isow7844fdwer.step / isow7844fdwer.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (58 pp, sha256 d52d56a624a0bade, retrieved 2026-09-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF