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Initial commit: component/isow7742fqdfmrq1

Ray ·038abbcacd ·5d ago
2 files changed +285
README.mdadded+56
@@ -0,0 +1,56 @@+# ISOW7742FQDFMRQ1++**Texas Instruments** · Digital Isolators (With Power) · SOIC-20++ISOW7742FQDFMRQ1 from Texas Instruments, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VIO | power_in | Side 1 logic supply, with a recommended range of 1.71 V to 5.5 V. |+| 2 | INA | input | Input channel A. |+| 3 | INB | input | Input channel B. |+| 4 | OUTC | output | Output channel C on ISOW7742-Q1. |+| 5 | OUTD | output | Output channel D. |+| 6 | GNDIO | power_in | Ground connection for VIO; GND1 and GNDIO need to be shorted on board. |+| 7 | EN_IO1 | input | Output Enable 1: high or open enables side 1 channel outputs; low puts them in high impedance and disables the side 1 input transmitters. |+| 8 | EN/FLT | bidirectional | Multi-function pin used either as power converter enable input (high to the VIO level enables, low at GND1 level disables) or as an active-low fault output needing a pull-up of 5 kΩ or greater. |+| 9 | VDD | power_in | Side 1 DC-DC converter power supply, with a range of 3 V to 5.5 V. |+| 10 | GND1 | power_in | Ground connection for VDD; GND1 and GNDIO need to be shorted on board. |+| 11 | GND2 | power_in | Ground connection for VISOOUT; GND2 and GISOIN can be shorted on board or connected through a ferrite bead. |+| 12 | VISOOUT | power_out | Isolated power converter output voltage; VISOIN and VISOOUT can be shorted on board or connected through a ferrite bead. |+| 13 | VSEL | input | VISOOUT selection pin: VISOOUT = 5 V when shorted to VISOOUT, 3.3 V when shorted to GND2. |+| 14 | EN_IO2 | input | Output Enable 2: high or open enables side 2 channel outputs; low puts them in high impedance and disables the side 2 input transmitters. |+| 15 | GISOIN | power_in | Ground connection for VISOIN; GND2 and GISOIN can be shorted on board or connected through a ferrite bead. |+| 16 | IND | input | Input channel D. |+| 17 | INC | input | Input channel C on ISOW7742-Q1. |+| 18 | OUTB | output | Output channel B. |+| 19 | OUTA | output | Output channel A. |+| 20 | VISOIN | power_in | Side 2 supply voltage for isolation channels; VISOIN and VISOOUT can be shorted on board or connected through a ferrite bead. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-20 |+| Category | Signal Isolation Devices |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `ISOW7742FQDFMRQ1`+- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`+- 3D model: SOIC-20 (KiCad packages3D, STEP)+- 3D model files: `isow7742fqdfmrq1-etched.step` / `isow7742fqdfmrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `isow7742fqdfmrq1.step` / `isow7742fqdfmrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8597547903233900544) (59 pp, sha256 `5f94cde786001b58`, retrieved 2026-10-03, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/isow7742fqdfmrq1-datasheet.pdf)
page.jsonadded+229
@@ -0,0 +1,229 @@+{+  "slug": "isow7742fqdfmrq1",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Digital Isolators (With Power), SOIC-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "signal isolation devices",+    "isow7742fqdfmrq1",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "isow7742fqdfmrq1.kicad_sym",+    "isow7742fqdfmrq1.kicad_mod",+    "isow7742fqdfmrq1.glb",+    "isow7742fqdfmrq1.step",+    "isow7742fqdfmrq1.lbr",+    "docs/hero.png",+    "docs/isow7742fqdfmrq1-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "isow7742fqdfmrq1-hero.glb",+    "isow7742fqdfmrq1-hero.overlay.json"+  ],+  "component": {+    "mpn": "ISOW7742FQDFMRQ1",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-20",+    "pin_count": 20,+    "category": "Signal Isolation Devices",+    "subcategory": "Digital Isolators (With Power)",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8597547903233900544",+    "parts": {+      "symbol": "isow7742fqdfmrq1.kicad_sym",+      "footprint": "isow7742fqdfmrq1.kicad_mod",+      "model_3d": "isow7742fqdfmrq1-hero.glb",+      "model_3d_plain": "isow7742fqdfmrq1.glb",+      "model_3d_step": "isow7742fqdfmrq1-etched.step",+      "model_3d_step_plain": "isow7742fqdfmrq1.step",+      "lbr": "isow7742fqdfmrq1.lbr"+    },+    "distributor_links": {+      "lcsc": 7290756,+      "digikey": "296-ISOW7742FQDFMRQ1TR-ND",+      "mouser": "595-ISOW7742FQDFMRQ1"+    },+    "distributor_check": {+      "checked_at": "2026-10-03T04:02:27Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-ISOW7742FQDFMRQ1TR-ND",+        "status": "found"+      },+      "mouser": {+        "pn": "595-ISOW7742FQDFMRQ1",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "VIO",+        "type": "power_in",+        "description": "Side 1 logic supply, with a recommended range of 1.71 V to 5.5 V."+      },+      {+        "number": "2",+        "name": "INA",+        "type": "input",+        "description": "Input channel A."+      },+      {+        "number": "3",+        "name": "INB",+        "type": "input",+        "description": "Input channel B."+      },+      {+        "number": "4",+        "name": "OUTC",+        "type": "output",+        "description": "Output channel C on ISOW7742-Q1."+      },+      {+        "number": "5",+        "name": "OUTD",+        "type": "output",+        "description": "Output channel D."+      },+      {+        "number": "6",+        "name": "GNDIO",+        "type": "power_in",+        "description": "Ground connection for VIO; GND1 and GNDIO need to be shorted on board."+      },+      {+        "number": "7",+        "name": "EN_IO1",+        "type": "input",+        "description": "Output Enable 1: high or open enables side 1 channel outputs; low puts them in high impedance and disables the side 1 input transmitters."+      },+      {+        "number": "8",+        "name": "EN/FLT",+        "type": "bidirectional",+        "description": "Multi-function pin used either as power converter enable input (high to the VIO level enables, low at GND1 level disables) or as an active-low fault output needing a pull-up of 5 kΩ or greater."+      },+      {+        "number": "9",+        "name": "VDD",+        "type": "power_in",+        "description": "Side 1 DC-DC converter power supply, with a range of 3 V to 5.5 V."+      },+      {+        "number": "10",+        "name": "GND1",+        "type": "power_in",+        "description": "Ground connection for VDD; GND1 and GNDIO need to be shorted on board."+      },+      {+        "number": "11",+        "name": "GND2",+        "type": "power_in",+        "description": "Ground connection for VISOOUT; GND2 and GISOIN can be shorted on board or connected through a ferrite bead."+      },+      {+        "number": "12",+        "name": "VISOOUT",+        "type": "power_out",+        "description": "Isolated power converter output voltage; VISOIN and VISOOUT can be shorted on board or connected through a ferrite bead."+      },+      {+        "number": "13",+        "name": "VSEL",+        "type": "input",+        "description": "VISOOUT selection pin: VISOOUT = 5 V when shorted to VISOOUT, 3.3 V when shorted to GND2."+      },+      {+        "number": "14",+        "name": "EN_IO2",+        "type": "input",+        "description": "Output Enable 2: high or open enables side 2 channel outputs; low puts them in high impedance and disables the side 2 input transmitters."+      },+      {+        "number": "15",+        "name": "GISOIN",+        "type": "power_in",+        "description": "Ground connection for VISOIN; GND2 and GISOIN can be shorted on board or connected through a ferrite bead."+      },+      {+        "number": "16",+        "name": "IND",+        "type": "input",+        "description": "Input channel D."+      },+      {+        "number": "17",+        "name": "INC",+        "type": "input",+        "description": "Input channel C on ISOW7742-Q1."+      },+      {+        "number": "18",+        "name": "OUTB",+        "type": "output",+        "description": "Output channel B."+      },+      {+        "number": "19",+        "name": "OUTA",+        "type": "output",+        "description": "Output channel A."+      },+      {+        "number": "20",+        "name": "VISOIN",+        "type": "power_in",+        "description": "Side 2 supply voltage for isolation channels; VISOIN and VISOOUT can be shorted on board or connected through a ferrite bead."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 8,+        "cost_usd": 0.0851,+        "at": "2026-10-03T04:02:02"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8597547903233900544",+        "pages": 59,+        "sha256": "5f94cde786001b58",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 20,+        "described": 20,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file