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ISO7742FDW

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Texas Instruments Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ISO7742FDW

Texas Instruments · Digital Isolators · SOIC-16-300mil

ISO7742FDW from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC1 power_in Power supply for side 1, recommended 2.25 V to 5.5 V (absolute maximum 6 V) with respect to GND1.
2 GND1 power_in Ground connection for VCC1.
3 INA input Input, channel A; high-level input threshold is 0.7 × VCCI and low-level is 0.3 × VCCI.
4 INB input Input, channel B; high-level input threshold is 0.7 × VCCI and low-level is 0.3 × VCCI.
5 OUTC output Output, channel C (side 1, driven from INC on side 2); rated for ±4 mA at VCCO = 5 V, ±2 mA at 3.3 V and ±1 mA at 2.5 V, and defaults low on loss of input power or signal for the F-suffix device.
6 OUTD output Output, channel D (side 1, driven from IND on side 2); rated for ±4 mA at VCCO = 5 V, ±2 mA at 3.3 V and ±1 mA at 2.5 V, and defaults low on loss of input power or signal for the F-suffix device.
7 EN1 input Output enable 1; output pins on side 1 are enabled when EN1 is high or open and in high-impedance state when EN1 is low.
8 GND1 power_in Ground connection for VCC1.
9 GND2 power_in Ground connection for VCC2.
10 EN2 input Output enable 2; output pins on side 2 are enabled when EN2 is high or open and in high-impedance state when EN2 is low.
11 IND input Input, channel D; high-level input threshold is 0.7 × VCCI and low-level is 0.3 × VCCI.
12 INC input Input, channel C; high-level input threshold is 0.7 × VCCI and low-level is 0.3 × VCCI.
13 OUTB output Output, channel B (side 2); rated for ±4 mA at VCCO = 5 V, ±2 mA at 3.3 V and ±1 mA at 2.5 V, and defaults low on loss of input power or signal for the F-suffix device.
14 OUTA output Output, channel A (side 2); rated for ±4 mA at VCCO = 5 V, ±2 mA at 3.3 V and ±1 mA at 2.5 V, and defaults low on loss of input power or signal for the F-suffix device.
15 GND2 power_in Ground connection for VCC2.
16 VCC2 power_in Power supply for side 2, recommended 2.25 V to 5.5 V (absolute maximum 6 V) with respect to GND2.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16-300mil
Category Communication Interface Chip/UART/485/232
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC1, VCC2 -0.5 6 V 8
Voltage at INx, OUTx, ENx V -0.5 V max = VCCX + 0.5, must not exceed 6 V 8
Output current IO -15 15 mA 8
Junction temperature TJ 150 °C 8
Storage temperature Tstg -65 150 °C 8
ESD HBM V(ESD) -6000 6000 V HBM per ANSI/ESDA/JEDEC JS-001, all pins 8
ESD CDM V(ESD) -1500 1500 V CDM per JESD22-C101, all pins 8
ESD IEC contact discharge V(ESD) -8000 8000 V Contact discharge per IEC 61000-4-2; isolation barrier withstand test 8
Supply voltage VCC1, VCC2 2.25 5.5 V 8
High-level output current IOH -4 mA VCCO = 5 V 8
High-level output current IOH -2 mA VCCO = 3.3 V 8
High-level output current IOH -1 mA VCCO = 2.5 V 8
Low-level output current IOL 4 mA VCCO = 5 V 8
Low-level output current IOL 2 mA VCCO = 3.3 V 8
Low-level output current IOL 1 mA VCCO = 2.5 V 8
Data rate DR 0 100 Mbps 8
Ambient temperature TA -55 25 125 °C 8
Junction-to-ambient thermal resistance RθJA 83.4 °C/W DW (SOIC) 16 pins 9
Junction-to-case (top) thermal resistance RθJC(top) 46 °C/W DW (SOIC) 16 pins 9
Junction-to-board thermal resistance RθJB 48 °C/W DW (SOIC) 16 pins 9
Junction-to-top characterization parameter ψJT 19.1 °C/W DW (SOIC) 16 pins 9
Junction-to-board characterization parameter ψJB 47.5 °C/W DW (SOIC) 16 pins 9
High-level output voltage VOH 4.8 V VCC1 = VCC2 = 5 V ±10%, IOH = -4 mA; min = VCCO, 0.4 12
Low-level output voltage VOL 0.2 0.4 V VCC1 = VCC2 = 5 V ±10%, IOL = 4 mA 12
High-level input current IIH 10 μA VCC = 5 V ±10%, VIH = VCCI at INx or ENx 12
Low-level input current IIL -10 μA VCC = 5 V ±10%, VIL = 0 V at INx or ENx 12
Common-mode transient immunity CMTI 85 100 kV/μs VCC = 5 V ±10%, VI = VCCI or 0 V, VCM = 1200 V 12
Input capacitance CI 2 pF VI = VCC/2 + 0.4×sin(2πft), f = 1 MHz, VCC = 5 V 12
High-level output voltage VOH 3.2 V VCC1 = VCC2 = 3.3 V ±10%, IOH = -2 mA; min = VCCO, 0.3 14
Low-level output voltage VOL 0.1 0.3 V VCC1 = VCC2 = 3.3 V ±10%, IOL = 2 mA 14
High-level input current IIH 10 μA VCC = 3.3 V ±10%, VIH = VCCI at INx or ENx 14
Low-level input current IIL -10 μA VCC = 3.3 V ±10%, VIL = 0 V at INx or ENx 14
Common-mode transient immunity CMTI 85 100 kV/μs VCC = 3.3 V ±10%, VI = VCCI or 0 V, VCM = 1200 V 14
High-level output voltage VOH 2.45 V VCC1 = VCC2 = 2.5 V ±10%, IOH = -1 mA; min = VCCO, 0.2 16
Low-level output voltage VOL 0.05 0.2 V VCC1 = VCC2 = 2.5 V ±10%, IOL = 1 mA 16
High-level input current IIH 10 μA VCC = 2.5 V ±10%, VIH = VCCI at INx or ENx 16
Low-level input current IIL -10 μA VCC = 2.5 V ±10%, VIL = 0 V at INx or ENx 16
Common-mode transient immunity CMTI 85 100 kV/μs VCC = 2.5 V ±10%, VI = VCCI or 0 V, VCM = 1200 V 16
Supply current - disable, F suffix (VI = VCCI) ICC1, ICC2 3 4.6 mA VCC = 5 V ±10%, EN1 = EN2 = 0 V; VI = VCCI (ISO7742 with F suffix) 13
Supply current - DC signal, F suffix (VI = VCCI) ICC1, ICC2 4 5.9 mA VCC = 5 V ±10%, EN1 = EN2 = VCCI; VI = VCCI (ISO7742 with F suffix) 13
Supply current - AC 1 Mbps ICC1, ICC2 3 4.4 mA VCC = 5 V ±10%, all channels switching with square wave clock input; CL = 15 pF 13
Supply current - AC 10 Mbps ICC1, ICC2 4 5.5 mA VCC = 5 V ±10%, all channels switching with square wave clock input; CL = 15 pF 13
Supply current - AC 100 Mbps ICC1, ICC2 13.4 17 mA VCC = 5 V ±10%, all channels switching with square wave clock input; CL = 15 pF 13
Propagation delay time tPLH, tPHL 6 10.7 16 ns VCC = 5 V ±10%, see Figure 15 18
Pulse width distortion PWD 0 4.9 ns VCC = 5 V ±10%, /tPHL, tPLH/ 18
Channel-to-channel output skew time tsk(o) 4 ns VCC = 5 V ±10%, same-direction channels 18
Part-to-part skew time tsk(pp) 4.4 ns VCC = 5 V ±10% 18
Output signal rise time tr 2.4 3.9 ns VCC = 5 V ±10%, see Figure 15 18
Output signal fall time tf 2.4 3.9 ns VCC = 5 V ±10%, see Figure 15 18

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing ppa • Changed the method b1 Vini condition for apparent charge in the Insulation Specifications table ...................................... 10 3

CAD (KiCad official)

  • Symbol: ISO7742FDW
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: iso7742fdw-etched.step / iso7742fdw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); iso7742fdw.step / iso7742fdw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (54 pp, sha256 6d75b03eef5cea97, retrieved 2026-10-23, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF