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ISO7421MDREP
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Texas Instruments Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownISO7421MDREP
Texas Instruments · Digital Isolators · SOIC-8
ISO7421MDREP from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC1 | power_in | Power supply for side 1; the datasheet specifies 3.0 V to 3.6 V for 3.3 V operation and 4.5 V to 5.5 V for 5 V operation. |
| 2 | OUTA | output | Channel A output, which drives at IOH of -4 mA maximum and IOL of 4 mA maximum per the recommended operating conditions. |
| 3 | INB | input | Channel B logic input with VIH of 2 V minimum and VIL of 0.8 V maximum, rated up to 5.25 V. |
| 4 | GND1 | power_in | Ground connection for VCC1 (side 1 ground). |
| 5 | GND2 | power_in | Ground connection for VCC2 (side 2 ground). |
| 6 | OUTB | output | Channel B output, which drives at IOH of -4 mA maximum and IOL of 4 mA maximum per the recommended operating conditions. |
| 7 | INA | input | Channel A logic input with VIH of 2 V minimum and VIL of 0.8 V maximum, rated up to 5.25 V. |
| 8 | VCC2 | power_in | Power supply for side 2; the datasheet specifies 3.0 V to 3.6 V for 3.3 V operation and 4.5 V to 5.5 V for 5 V operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC1, VCC2 | VCC | -0.5 | 6 | V | 4 | ||
| Voltage at IN, OUT | VI | -0.5 | V | max VCC + 0.5 V; must not exceed 6 V | 4 | ||
| Output current | IO | -15 | 15 | mA | 4 | ||
| Maximum junction temperature | TJ(max) | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Supply voltage, 3.3-V operation | VCC1, VCC2 | 3 | 3.3 | 3.6 | V | 4 | |
| Supply voltage, 5-V operation | VCC1, VCC2 | 4.5 | 5 | 5.5 | V | 4 | |
| High-level input voltage | VIH | 2 | 5.25 | V | 4 | ||
| Low-level input voltage | VIL | 0 | 0.8 | V | 4 | ||
| Signaling rate | 1/tui | 0 | 1 | Mbps | 4 | ||
| Junction temperature | TJ | -55 | 136 | °C | 4 | ||
| High-level output current | IOH | -4 | mA | 4 | |||
| Low-level output current | IOL | 4 | mA | 4 | |||
| Input pulse duration | tui | 1 | μs | 4 | |||
| Input threshold voltage hysteresis (5 V) | VI(HYS) | 400 | mV | VCC1 and VCC2 at 5 V ±10% | 5 | ||
| High-level input current | IIH | 10 | μA | INx at 0 V or VCCI | 5 | ||
| Low-level input current | IIL | -10 | μA | INx at 0 V or VCCI | 5 | ||
| Common-mode transient immunity (5 V) | CMTI | 25 | 50 | kV/μs | VI = VCCI or 0 V; see Figure 8. | 5 | |
| Supply current for VCC1 (5 V) | ICC1 | 2 | 4 | mA | DC to 1 Mbps; VI = VCCI or 0 V, 15 pF load | 5 | |
| Supply current for VCC2 (5 V) | ICC2 | 2 | 4 | mA | DC to 1 Mbps; VI = VCCI or 0 V, 15 pF load | 5 | |
| Propagation delay time (5 V) | tPLH, tPHL | 9 | 14 | ns | See Figure 6. | 7 | |
| Pulse width distortion (5 V) | PWD | 0.3 | 4 | ns | /tPHL, tPLH/ | 7 | |
| Part-to-part skew time (5 V) | tsk(pp) | 4.9 | ns | 7 | |||
| Channel-to-channel output skew time (5 V) | tsk(o) | 3.6 | ns | 7 | |||
| Output signal rise time (5 V) | tr | 1 | ns | See Figure 6. | 7 | ||
| Output signal fall time (5 V) | tf | 1 | ns | 7 | |||
| Fail-safe output delay time from input power loss (5 V) | tfs | 6 | μs | See Figure 7. | 7 | ||
| Safety input, output, or supply current (5.25 V) | IS | 112 | mA | RθJA = 212°C/W, VI = 5.25 V, TJ = 150°C, TA = 25°C | 12 | ||
| Safety input, output, or supply current (3.45 V) | IS | 171 | mA | RθJA = 212°C/W, VI = 3.45 V, TJ = 150°C, TA = 25°C | 12 | ||
| Maximum safety temperature | TS | 150 | °C | 12 | |||
| Device power dissipation | PD | 55 | mW | VCC1 = VCC2 = 5.25 V, TJ = 150°C, CL = 15 pF, input 1-Mbps 50% duty-cycle square wave | 6 | ||
| Junction-to-ambient thermal resistance, low-K board | RθJA | 212 | °C/W | Low-K Board | 4 | ||
| Junction-to-ambient thermal resistance, high-K board | RθJA | 116.6 | °C/W | High-K Board | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 71.6 | °C/W | 4 | |||
| Junction-to-board thermal resistance | RθJB | 57.3 | °C/W | 4 | |||
| Junction-to-top characterization parameter | ψJT | 28.3 | °C/W | 4 | |||
| Junction-to-board characterization parameter | ψJB | 56.8 | °C/W | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | VIORM Maximum working insulation voltage 566 VPK VPR Input-to-output test voltage t = 1 s (100% production), partial discharge 5 pC 1062 VPK | 11 |
CAD (KiCad official)
- Symbol:
ISO7421MDREP - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
iso7421mdrep-etched.step/iso7421mdrep-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);iso7421mdrep.step/iso7421mdrep.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (24 pp, sha256
932074045d14ee72, retrieved 2026-10-28, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).