# ISO7420EDR

**Texas Instruments** · Digital Isolators · SOIC-8

ISO7420EDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC1 | power_in | Power supply for side 1 (input side), recommended 3.0 V to 5.5 V with respect to GND1. |
| 2 | INA | input | Channel A input with TTL thresholds (VIH 2 V min, VIL 0.8 V max), 5.5 V maximum recommended input voltage. |
| 3 | INB | input | Channel B input with TTL thresholds (VIH 2 V min, VIL 0.8 V max), 5.5 V maximum recommended input voltage. |
| 4 | GND1 | power_in | Ground connection for VCC1. |
| 5 | GND2 | power_in | Ground connection for VCC2. |
| 6 | OUTB | output | Channel B output, rated for ±4 mA recommended high/low-level output current. |
| 7 | OUTA | output | Channel A output, rated for ±4 mA recommended high/low-level output current. |
| 8 | VCC2 | power_in | Power supply for side 2 (output side), recommended 3.0 V to 5.5 V with respect to GND2. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC1, VCC2 | -0.5 |  | 6 | V |  | 5 |
| Voltage at IN, OUT | VI | -0.5 |  |  | V | max VCC + 0.5, must not exceed 6 V | 5 |
| Output current | IO | -15 |  | 15 | mA |  | 5 |
| Maximum surge immunity | VSRG |  |  | 4000 | VPK | Supports IEC 61000-4-5 | 5 |
| Maximum junction temperature | TJ(Max) |  |  | 150 | °C |  | 5 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 5 |
| ESD HBM | V(ESD) | -3000 |  | 3000 | V | ANSI/ESDA/JEDEC JS-001 | 5 |
| ESD CDM | V(ESD) | -1500 |  | 1500 | V | JESD22-C101 | 5 |
| ESD MM | V(ESD) | -200 |  | 200 | V | ANSI/ESDS5.2-1996 | 5 |
| Supply voltage | VCC1, VCC2 | 3 |  | 5.5 | V |  | 5 |
| High-level output current | IOH | -4 |  |  | mA |  | 5 |
| Low-level output current | IOL |  |  | 4 | mA |  | 5 |
| High-level input voltage | VIH | 2 |  | 5.5 | V |  | 5 |
| Low-level input voltage | VIL | 0 |  | 0.8 | V |  | 5 |
| Input pulse duration | tui | 20 |  |  | ns |  | 5 |
| Signaling rate | 1 / tui | 0 |  | 50 | Mbps | Under typical conditions capable of > 150 Mbps | 5 |
| Junction temperature | TJ | -40 |  | 136 | °C |  | 5 |
| Ambient temperature | TA | -40 | 25 | 125 | °C |  | 5 |
| Junction-to-ambient thermal resistance, low-K board | RθJA |  | 212 |  | °C/W | D (SOIC) 8 pins, Low-K board | 5 |
| Junction-to-ambient thermal resistance, high-K board | RθJA |  | 116.6 |  | °C/W | D (SOIC) 8 pins, High-K board | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 71.6 |  | °C/W |  | 5 |
| Junction-to-board thermal resistance | RθJB |  | 57.3 |  | °C/W |  | 5 |
| Junction-to-top characterization parameter | ψJT |  | 28.3 |  | °C/W |  | 5 |
| Junction-to-board characterization parameter | ψJB |  | 56.8 |  | °C/W |  | 5 |
| High-level output voltage | VOH |  | 4.6 |  | V | IOH = -4 mA; min is VCCO, 0.8; VCC1 and VCC2 = 5 V ± 10% | 6 |
| High-level output voltage | VOH |  | 5 |  | V | IOH = -20 μA; min is VCCO, 0.1; VCC1 and VCC2 = 5 V ± 10% | 6 |
| Low-level output voltage | VOL |  | 0.2 | 0.4 | V | IOL = 4 mA; VCC1 and VCC2 = 5 V ± 10% | 6 |
| Low-level output voltage | VOL |  | 0 | 0.1 | V | IOL = 20 μA; VCC1 and VCC2 = 5 V ± 10% | 6 |
| Input threshold voltage hysteresis | VI(HYS) |  | 400 |  | mV | VCC1 and VCC2 = 5 V ± 10% | 6 |
| High-level input current | IIH |  |  | 10 | μA | INx at 0 V or VCCI | 6 |
| Low-level input current | IIL | -10 |  |  | μA | INx at 0 V or VCCI | 6 |
| Common-mode transient immunity | CMTI | 25 | 50 |  | kV/μs | VI = VCCI or 0 V; see Figure 18 | 6 |
| Supply current ICC1, DC | ICC1 |  | 0.4 | 0.8 | mA | ISO7420x, DC to 1 Mbps, VI = VCCI or 0 V; 5 V | 6 |
| Supply current ICC2, DC | ICC2 |  | 3.4 | 5 | mA | ISO7420x, DC to 1 Mbps, VI = VCCI or 0 V; 5 V | 6 |
| Supply current ICC1, 10 Mbps | ICC1 |  | 0.6 | 1 | mA | ISO7420x, 10 Mbps, CL = 15 pF; 5 V | 6 |
| Supply current ICC2, 10 Mbps | ICC2 |  | 4.5 | 6 | mA | ISO7420x, 10 Mbps, CL = 15 pF; 5 V | 6 |
| Supply current ICC1, 25 Mbps | ICC1 |  | 1 | 1.5 | mA | ISO7420x, 25 Mbps, CL = 15 pF; 5 V | 6 |
| Supply current ICC2, 25 Mbps | ICC2 |  | 6.2 | 8 | mA | ISO7420x, 25 Mbps, CL = 15 pF; 5 V | 6 |
| Supply current ICC1, 50 Mbps | ICC1 |  | 1.7 | 2.5 | mA | ISO7420x, 50 Mbps, CL = 15 pF; 5 V | 6 |
| Supply current ICC2, 50 Mbps | ICC2 |  | 9 | 12 | mA | ISO7420x, 50 Mbps, CL = 15 pF; 5 V | 6 |
| Propagation delay time | tPLH, tPHL |  | 7 | 11 | ns | See Figure 16; VCC1 and VCC2 = 5 V ± 10% | 10 |
| Pulse width distortion /tPHL, tPLH/ | PWD |  | 0.2 | 3 | ns | ISO7420x; VCC1 and VCC2 = 5 V ± 10% | 10 |
| Channel-to-channel output skew time | tsk(o) |  | 0.3 | 1 | ns | ISO7420x; VCC1 and VCC2 = 5 V ± 10% | 10 |
| Part-to-part skew time | tsk(pp) |  |  | 3.7 | ns | ISO7420x; VCC1 and VCC2 = 5 V ± 10% | 10 |
| Output signal rise time | tr |  | 1.8 |  | ns | See Figure 16; VCC1 and VCC2 = 5 V ± 10% | 10 |
| Output signal fall time | tf |  | 1.7 |  | ns | See Figure 16; VCC1 and VCC2 = 5 V ± 10% | 10 |
| Fail-safe output delay time from input power loss | tfs |  |  | 6 | μs | See Figure 17; VCC1 and VCC2 = 5 V ± 10% | 10 |
| Device power dissipation | PD |  |  | 138 | mW | VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 100-Mbps 50% duty-cycle square wave | 9 |
| High-level output voltage | VOH |  | 3 |  | V | IOH = -4 mA; min is VCCO, 0.4; VCC1 and VCC2 = 3.3 V ± 10% | 9 |
| High-level output voltage | VOH |  | 3.3 |  | V | IOH = -20 μA; min is VCCO, 0.1; VCC1 and VCC2 = 3.3 V ± 10% | 9 |
| Supply current ICC1, DC | ICC1 |  | 0.2 | 0.4 | mA | ISO7420x, DC to 1 Mbps, VI = VCCI or 0 V; 3.3 V | 9 |
| Supply current ICC2, DC | ICC2 |  | 2.6 | 3.7 | mA | ISO7420x, DC to 1 Mbps, VI = VCCI or 0 V; 3.3 V | 9 |
| Supply current ICC1, 50 Mbps | ICC1 |  | 1 | 1.3 | mA | ISO7420x, 50 Mbps, CL = 15 pF; 3.3 V | 9 |
| Supply current ICC2, 50 Mbps | ICC2 |  | 6.2 | 7.5 | mA | ISO7420x, 50 Mbps, CL = 15 pF; 3.3 V | 9 |
| Propagation delay time | tPLH, tPHL |  | 8.5 | 14 | ns | See Figure 16; VCC1 and VCC2 = 3.3 V ± 10% | 11 |
| Pulse width distortion /tPHL, tPLH/ | PWD |  | 0.5 | 2 | ns | ISO7420x and ISO7421x; VCC1 and VCC2 = 3.3 V ± 10% | 11 |
| Maximum withstand isolation voltage | VISO |  | 2500 |  | VRMS | UL 1577, VTEST = VISO = 2500 VRMS, t = 60 sec | 18 |

## CAD (KiCad official)

- Symbol: `ISO7420EDR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `iso7420edr-etched.step` / `iso7420edr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `iso7420edr.step` / `iso7420edr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/iso7420e.pdf) (35 pp, sha256 `fd2697d2a8652c8e`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/iso7420edr-datasheet.pdf)