component

ISO7320CDR

Public Made by Adom

by adom

Texas Instruments Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232iso7320cdrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

ISO7320CDR

Texas Instruments · Digital Isolators · SOIC-8

ISO7320CDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC1 power_in Side-1 power supply, recommended 3 V to 5.5 V (absolute maximum 6 V) with respect to GND1.
2 INA input Channel A input on side 1 (ISO7320), with TTL thresholds (VIH min 2 V, VIL max 0.8 V) and an integrated noise filter.
3 INB input Channel B input on side 1, with TTL thresholds (VIH min 2 V, VIL max 0.8 V) and an integrated noise filter.
4 GND1 power_in Ground connection for VCC1 (side 1).
5 GND2 power_in Ground connection for VCC2 (side 2).
6 OUTB output Channel B output on side 2, rated for recommended high/low-level output current of -4 mA / 4 mA.
7 OUTA output Channel A output on side 2 (ISO7320), rated for recommended high/low-level output current of -4 mA / 4 mA.
8 VCC2 power_in Side-2 power supply, recommended 3 V to 5.5 V (absolute maximum 6 V) with respect to GND2.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Communication Interface Chip/UART/485/232
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC1, VCC2 -0.5 6 V 4
Voltage INx, OUTx -0.5 5.5 V VCC + 0.5, must not exceed 6 V 4
Output current IO -15 15 mA ±15 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
ESD HBM VESD -4000 4000 V HBM per ANSI/ESDA/JEDEC JS-001 4
ESD CDM VESD -1500 1500 V CDM per JESD22-C101 4
Supply voltage VCC1, VCC2 3 5.5 V 4
High-level output current IOH -4 mA 4
Low-level output current IOL 4 mA 4
High-level input voltage VIH 2 5.5 V 4
Low-level input voltage VIL 0 0.8 V 4
Input pulse duration tui 40 ns 4
Signaling rate 1/tui 0 25 Mbps 4
Junction temperature TJ 136 °C 4
Ambient temperature TA -40 25 125 °C 4
Junction-to-ambient thermal resistance RθJA 121 °C/W D package, 8 pins 4
Junction-to-case (top) thermal resistance RθJCtop 67.9 °C/W 4
Junction-to-board thermal resistance RθJB 61.6 °C/W 4
Junction-to-top characterization parameter ψJT 21.5 °C/W 4
Junction-to-board characterization parameter ψJB 61.1 °C/W 4
Max power dissipation ISO7320 PD 56 mW VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 12.5 MHz 50% duty-cycle square wave 4
Max power dissipation side-1 ISO7320 PD1 15 mW VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 12.5 MHz 50% duty-cycle square wave 4
Max power dissipation side-2 ISO7320 PD2 41 mW VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 12.5 MHz 50% duty-cycle square wave 4
High-level output voltage (5 V) VOH 4.7 V IOH = -4 mA; see Figure 11; VCCO, 0.5 min; VCC 5 V ± 10% 5
High-level output voltage (5 V) VOH 5 V IOH = -20 μA; see Figure 11; VCCO, 0.1 min; VCC 5 V ± 10% 5
Low-level output voltage (5 V) VOL 0.2 0.4 V IOL = 4 mA; see Figure 11; VCC 5 V ± 10% 5
Low-level output voltage (5 V) VOL 0 0.1 V IOL = 20 μA; see Figure 11; VCC 5 V ± 10% 5
Input threshold voltage hysteresis (5 V) VI(HYS) 460 mV VCC 5 V ± 10% 5
High-level input current (5 V) IIH 10 μA IN = VCC; VCC 5 V ± 10% 5
Low-level input current (5 V) IIL -10 μA IN = 0 V; VCC 5 V ± 10% 5
Common-mode transient immunity (5 V) CMTI 25 65 kV/μs VI = VCC or 0 V; see Figure 13; VCC 5 V ± 10% 5
ICC1 DC to 1 Mbps (5 V) ICC1 0.4 0.9 mA ISO7320, DC Input: VI = VCC or 0 V 5
ICC2 DC to 1 Mbps (5 V) ICC2 2 3.2 mA ISO7320, DC Input: VI = VCC or 0 V 5
ICC1 10 Mbps (5 V) ICC1 0.8 1.4 mA ISO7320, AC Input, CL = 15pF 5
ICC2 10 Mbps (5 V) ICC2 3.2 4.4 mA ISO7320, AC Input, CL = 15pF 5
ICC1 25 Mbps (5 V) ICC1 1.4 2.3 mA ISO7320, AC Input, CL = 15pF 5
ICC2 25 Mbps (5 V) ICC2 4.9 6.8 mA ISO7320, AC Input, CL = 15pF 5
High-level output voltage (3.3 V) VOH 3 V IOH = -4 mA; see Figure 11; VCCO, 0.5 min; VCC 3.3 V ± 10% 5
High-level output voltage (3.3 V) VOH 3.3 V IOH = -20 μA; see Figure 11; VCCO, 0.1 min; VCC 3.3 V ± 10% 5
Low-level output voltage (3.3 V) VOL 0.2 0.4 V IOL = 4 mA; see Figure 11; VCC 3.3 V ± 10% 5
Low-level output voltage (3.3 V) VOL 0 0.1 V IOL = 20 μA; see Figure 11; VCC 3.3 V ± 10% 5
Input threshold voltage hysteresis (3.3 V) VI(HYS) 450 mV VCC 3.3 V ± 10% 5
High-level input current (3.3 V) IIH 10 μA IN = VCC; VCC 3.3 V ± 10% 5
Low-level input current (3.3 V) IIL -10 μA IN = 0 V; VCC 3.3 V ± 10% 5
Common-mode transient immunity (3.3 V) CMTI 25 50 kV/μs VI = VCC or 0 V; see Figure 13; VCC 3.3 V ± 10% 5
ICC1 DC to 1 Mbps (3.3 V) ICC1 0.2 0.5 mA ISO7320, DC Input: VI = VCC or 0 V 5
ICC2 DC to 1 Mbps (3.3 V) ICC2 1.5 2.5 mA ISO7320, DC Input: VI = VCC or 0 V 5
ICC1 10 Mbps (3.3 V) ICC1 0.5 0.8 mA ISO7320, AC Input, CL = 15pF 5
ICC2 10 Mbps (3.3 V) ICC2 2.2 3.2 mA ISO7320, AC Input, CL = 15pF 5
ICC1 25 Mbps (3.3 V) ICC1 0.9 1.4 mA ISO7320, AC Input, CL = 15pF 5
ICC2 25 Mbps (3.3 V) ICC2 3.3 4.7 mA ISO7320, AC Input, CL = 15pF 5
Propagation delay time (5 V) tPLH, tPHL 20 33 57 ns See Figure 11; VCC 5 V ± 10% 6
Pulse width distortion (5 V) PWD 4 ns /tPHL, tPLH/ 6
Channel-to-channel output skew (5 V) tsk(o) 2 ns ISO7320 6
Part-to-part skew (5 V) tsk(pp) 23 ns 6
Output signal rise time (5 V) tr 2.4 ns See Figure 11 6
Output signal fall time (5 V) tf 2.1 ns See Figure 11 6
Fail-safe output delay time (5 V) tfs 7.5 μs See Figure 12 6
Propagation delay time (3.3 V) tPLH, tPHL 22 37 66 ns See Figure 11; VCC 3.3 V ± 10% 6
Pulse width distortion (3.3 V) PWD 3 ns /tPHL, tPLH/ 6
Channel-to-channel output skew (3.3 V) tsk(o) 3 ns ISO7320 6
Part-to-part skew (3.3 V) tsk(pp) 28 ns 6
Output signal rise time (3.3 V) tr 3.1 ns See Figure 11 6
Output signal fall time (3.3 V) tf 2.6 ns See Figure 11 6
Fail-safe output delay time (3.3 V) tfs 7.4 μs See Figure 12 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pet Voltage, 6000 V 300 VRMS Basic Insulation PK maximum working voltage Maximum Repetitive Peak working voltage per CSA 12

CAD (KiCad official)

  • Symbol: ISO7320CDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: iso7320cdr-etched.step / iso7320cdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); iso7320cdr.step / iso7320cdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 f9bd7328fdfb068b, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF