main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers iso7021fdr: viewers · Ray 2d ago
iso7021fdr-etched.glb iso7021fdr: factory component page (tier=lcsc) · Ray 2d ago
iso7021fdr-etched.step iso7021fdr: factory component page (tier=lcsc) · Ray 2d ago
iso7021fdr-hero.glb Publish 0.1.0 · Ray 2d ago
iso7021fdr-hero.overlay.json Publish 0.1.0 · Ray 2d ago
iso7021fdr.glb Publish 0.1.0 · Ray 2d ago
iso7021fdr.kicad_mod Publish 0.1.0 · Ray 2d ago
iso7021fdr.kicad_sym Publish 0.1.0 · Ray 2d ago
iso7021fdr.lbr Publish 0.1.0 · Ray 2d ago
iso7021fdr.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Initial commit: component/iso7021fdr · Ray 2d ago

ISO7021FDR

Texas Instruments · Digital Isolators · SOIC-8

ISO7021FDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC1 power_in Power supply for side 1 of the isolation barrier.
2 OUTA output Output channel A with high-level voltage VCCO - 0.4V and low-level voltage 0.4V.
3 INB input Input channel B with switching threshold 0.3V to 0.7V × VCCI.
4 GND1 power_in Ground connection for VCC1.
5 GND2 power_in Ground connection for VCC2.
6 OUTB output Output channel B with high-level voltage VCCO - 0.4V and low-level voltage 0.4V.
7 INA input Input channel A with switching threshold 0.3V to 0.7V × VCCI.
8 VCC2 power_in Power supply for side 2 of the isolation barrier.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Signal Isolation Devices
Pins 8

CAD (KiCad official)

  • Symbol: ISO7021FDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: iso7021fdr-etched.step / iso7021fdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); iso7021fdr.step / iso7021fdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 6bd32f3a3baf3002, retrieved 2026-10-03, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF