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ISO6762FQDWRQ1
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Texas Instruments Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownISO6762FQDWRQ1
Texas Instruments · Digital Isolators · SOIC-16
ISO6762FQDWRQ1 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC1 | power_in | Power supply, side 1 (1.71V to 1.89V or 2.25V to 5.5V recommended range; absolute maximum 6 V with respect to GND1). |
| 2 | INA | input | Input, channel A. |
| 3 | INB | input | Input, channel B. |
| 4 | INC | input | Input, channel C. |
| 5 | IND | input | Input, channel D. |
| 6 | OUTE | output | Output, channel E. |
| 7 | OUTF | output | Output, channel F. |
| 8 | GND1 | power_in | Ground connection for VCC1. |
| 9 | GND2 | power_in | Ground connection for VCC2. |
| 10 | INF | input | Input, channel F. |
| 11 | INE | input | Input, channel E. |
| 12 | OUTD | output | Output, channel D. |
| 13 | OUTC | output | Output, channel C. |
| 14 | OUTB | output | Output, channel B. |
| 15 | OUTA | output | Output, channel A. |
| 16 | VCC2 | power_in | Power supply, side 2 (1.71V to 1.89V or 2.25V to 5.5V recommended range; absolute maximum 6 V with respect to GND2). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC1 | VCC1 | -0.5 | 6 | V | VCC1 to GND1 | 5 | |
| Supply voltage VCC2 | VCC2 | -0.5 | 6 | V | VCC2 to GND2 | 5 | |
| Output current | Io | -15 | 15 | mA | 5 | ||
| Operating junction temperature | TJ | 150 | °C | 5 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | Human body model, ANSI/ESDA/JEDEC JS-001, all pins | 5 | |
| ESD CDM | V(ESD) | -1500 | 1500 | V | Charged device model, JESD22-C101, all pins | 5 | |
| Supply voltage side 1 (low range) | VCC1 | 1.71 | 1.89 | V | 6 | ||
| Supply voltage side 1 (high range) | VCC1 | 2.25 | 5.5 | V | 6 | ||
| Supply voltage side 2 (low range) | VCC2 | 1.71 | 1.89 | V | 6 | ||
| Supply voltage side 2 (high range) | VCC2 | 2.25 | 5.5 | V | 6 | ||
| Data rate | DR | 0 | 50 | Mbps | 6 | ||
| Ambient temperature | TA | -40 | 25 | 125 | °C | 6 | |
| High level output current | IOH | -4 | mA | VCCO = 5 V | 6 | ||
| Low level output current | IOL | 4 | mA | VCCO = 5 V | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 68.8 | °C/W | DW (SOIC) 16 pins | 7 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 31.8 | °C/W | DW (SOIC) 16 pins | 7 | ||
| Junction-to-board thermal resistance | RθJB | 32.7 | °C/W | DW (SOIC) 16 pins | 7 | ||
| Junction-to-top characterization parameter | ψJT | 13.5 | °C/W | DW (SOIC) 16 pins | 7 | ||
| Junction-to-board characterization parameter | ψJB | 32.1 | °C/W | DW (SOIC) 16 pins | 7 | ||
| Low-level output voltage | VOL | 0.4 | V | IOL = 4 mA; 5-V supply | 10 | ||
| High-level input current | IIH | 10 | µA | VIH = VCCI at INx; 5-V supply | 10 | ||
| Low-level input current | IIL | -10 | µA | VIL = 0 V at INx; 5-V supply | 10 | ||
| Common mode transient immunity | CMTI | 100 | 150 | kV/us | VI = VCC or 0 V, VCM = 1200 V; 5-V supply | 10 | |
| Common mode transient immunity | CMTI | 50 | 75 | kV/us | VI = VCC or 0 V, VCM = 1200 V; 1.8-V supply | 16 | |
| Input capacitance | Ci | 2.8 | pF | VI = VCC/2 + 0.4×sin(2πft), f = 2 MHz, VCC = 5 V | 10 | ||
| ICC1 DC signal, VI = VCC1 (VI = 0 V for F suffix) | ICC1 | 2.7 | 4.1 | mA | ISO6762, 5 V ±10% | 11 | |
| ICC2 DC signal, VI = VCC1 (VI = 0 V for F suffix) | ICC2 | 3.3 | 5.2 | mA | ISO6762, 5 V ±10% | 11 | |
| ICC1 DC signal, VI = 0 V (VI = VCC1 for F suffix) | ICC1 | 6.9 | 9.7 | mA | ISO6762, 5 V ±10% | 11 | |
| ICC2 DC signal, VI = 0 V (VI = VCC1 for F suffix) | ICC2 | 5.6 | 8.3 | mA | ISO6762, 5 V ±10% | 11 | |
| ICC1 AC 1 Mbps | ICC1 | 5 | 7 | mA | ISO6762, all channels switching, CL = 15 pF, 5 V ±10% | 11 | |
| ICC2 AC 1 Mbps | ICC2 | 4.7 | 7 | mA | ISO6762, all channels switching, CL = 15 pF, 5 V ±10% | 11 | |
| ICC1 AC 10 Mbps | ICC1 | 6.2 | 8.4 | mA | ISO6762, all channels switching, CL = 15 pF, 5 V ±10% | 11 | |
| ICC2 AC 10 Mbps | ICC2 | 7 | 9.6 | mA | ISO6762, all channels switching, CL = 15 pF, 5 V ±10% | 11 | |
| ICC1 AC 50 Mbps | ICC1 | 11.7 | 14.6 | mA | ISO6762, all channels switching, CL = 15 pF, 5 V ±10% | 11 | |
| ICC2 AC 50 Mbps | ICC2 | 17.2 | 21.1 | mA | ISO6762, all channels switching, CL = 15 pF, 5 V ±10% | 11 | |
| Propagation delay time | tPLH, tPHL | 11 | 18 | ns | See Figure 7-1; 5-V supply | 18 | |
| Pulse width distortion | PWD | 7 | ns | /tPHL, tPLH/; 5-V supply | 18 | ||
| Channel-to-channel output skew time | tsk(o) | 6 | ns | Same-direction channels; 5-V supply | 18 | ||
| Part-to-part skew time | tsk(pp) | 6 | ns | 5-V supply | 18 | ||
| Output signal rise time | tr | 4.5 | ns | See Figure 7-1; 5-V supply | 18 | ||
| Output signal fall time | tf | 4.5 | ns | See Figure 7-1; 5-V supply | 18 | ||
| Time from UVLO to valid output data | tPU | 300 | us | 5-V supply | 18 | ||
| Default output delay time from input power loss | tDO | 0.1 | 0.3 | us | Measured from the time VCC goes below 1.2V. See Figure 7-2; 5-V supply | 18 | |
| Propagation delay time, 3.3-V supply | tPLH, tPHL | 11 | 18 | ns | See Figure 7-1; 3.3-V supply | 19 | |
| Propagation delay time, 1.8-V supply | tPLH, tPHL | 15 | 24 | ns | See Figure 7-1; 1.8-V supply | 21 | |
| Time interval error | tie | 1 | ns | 2^16, 1 PRBS data at 50 Mbps; 5-V supply | 18 | ||
| Maximum power dissipation (both sides), ISO6762 | PD | 197 | mW | VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 25-MHz 50% duty cycle square wave | 7 | ||
| Maximum withstanding isolation voltage | VISO | 5000 | VRMS | VTEST = VISO, t = 60 s (qualification), VTEST = 1.2 x VISO, t = 1 s (100% production) | 8 |
CAD (KiCad official)
- Symbol:
ISO6762FQDWRQ1 - Footprint:
Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
iso6762fqdwrq1-etched.step/iso6762fqdwrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);iso6762fqdwrq1.step/iso6762fqdwrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
6b73c29575e017fa, retrieved 2026-10-27, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).