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ISO5851DWR

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Texas Instruments Gate Drive ICs, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ISO5851DWR

Texas Instruments · Gate Drive ICs · SOIC-16-300mil

ISO5851DWR from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VEE2 power_in Output negative supply; connect to GND2 for unipolar supply applications (recommended VEE2 -15 V to 0 V relative to GND2).
2 DESAT input Desaturation voltage input for IGBT overload detection, rated GND2 - 0.3 V to VCC2 + 0.3 V.
3 GND2 power_in Gate drive common; connect to IGBT emitter.
4 NC unconnected Not connected.
5 VCC2 power_in Most positive output supply potential, recommended 15 V to 30 V relative to GND2.
6 OUT output Gate drive voltage output with 2.5 A peak source and 5 A peak sink capability.
7 CLAMP output Miller clamp output designed for Miller current up to 2 A, activated when gate voltage falls below 2 V at turn-off.
8 VEE2 power_in Output negative supply; connect to GND2 for unipolar supply applications (recommended VEE2 -15 V to 0 V relative to GND2).
9 GND1 power_in Input ground.
10 IN+ input Non-inverting gate drive voltage control input with CMOS-compatible thresholds (VIH 0.7 × VCC1, VIL 0.3 × VCC1).
11 IN- input Inverting gate drive voltage control input with CMOS-compatible thresholds (VIH 0.7 × VCC1, VIL 0.3 × VCC1).
12 RDY output Power-good output, active high when both input and output supplies are good.
13 FLT output Fault output, low-active during DESAT condition and latched until reset by RST.
14 RST input Reset input; apply a low pulse of at least 800 ns to reset the fault latch.
15 VCC1 power_in Positive input supply, 3 V to 5.5 V.
16 GND1 power_in Input ground.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16-300mil
Category Power Supply Chip
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage input side VCC1 -0.3 6 V GND1, 0.3 to 6 6
Positive supply voltage output side VCC2 -0.3 35 V VCC2, GND2 6
Negative supply voltage output side VEE2 -17.5 0.3 V VEE2, GND2 6
Total supply output voltage V(SUP2) -0.3 35 V VCC2, VEE2 6
Gate driver high output current I(OUTH) 2.7 A max pulse width = 10 μs, max duty cycle = 0.2% 6
Gate driver low output current I(OUTL) 5.5 A max pulse width = 10 μs, max duty cycle = 0.2% 6
Output current of FLT, RDY I(LOP) 10 mA 6
Junction temperature TJ -40 150 °C 6
Storage temperature TSTG -65 150 °C 6
ESD HBM V(ESD) -4000 4000 V Human body model, ANSI/ESDA/JEDEC JS-001 6
ESD CDM V(ESD) -1500 1500 V Charged-device model, JESD22-C101 6
Supply voltage input side VCC1 3 5.5 V 6
Positive supply voltage output side VCC2 15 30 V VCC2, GND2 6
Negative supply voltage output side VEE2 -15 0 V VEE2, GND2 6
Total supply voltage output side V(SUP2) 15 30 V VCC2, VEE2 6
Pulse width at IN+, IN- for full output tUI 40 ns CLOAD = 1 nF 6
Pulse width at RST for resetting fault latch tRST 800 ns 6
Ambient temperature TA -40 25 125 °C 6
Junction-to-ambient thermal resistance RθJA 99.6 °C/W DW (SOIC) 16 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 48.5 °C/W 7
Junction-to-board thermal resistance RθJB 56.5 °C/W 7
Maximum power dissipation PD 1255 mW 7
Input supply quiescent current IQ1 2.8 4.5 mA 10
Output supply quiescent current IQ2 3.6 6 mA 10
High-level input leakage at (IN+) IIH 100 µA IN+ = VCC1 10
Low-level input leakage at (IN-, RST) IIL -100 µA IN- = GND1, RST = GND1 10
Low-level output voltage at FLT, RDY VOL 0.2 V I(FLT) = 5 mA 10
Active output pulldown voltage V(OUTPD) 2 V IOUT = 200 mA, VCC2 = open 10
High-level output peak current I(OUTH) 1.5 2.5 A IN+ = high, IN- = low, VOUT = VCC2 - 15 V 10
Low-level output peak current I(OUTL) 3.4 5 A IN+ = low, IN- = high, VOUT = VEE2 + 15 V 10
Low-level clamp current I(CLP) 1.6 2.5 A V(CLAMP) = VEE2 + 2.5 V 10
Clamp threshold voltage V(CLTH) 1.6 2.1 2.5 V 10
Clamping voltage (VOUT - VCC2) V(CLP_OUT) 0.8 1.3 V IN+ = high, IN- = low, tCLP = 10 µs, I(OUTH) = 500 mA 10
Clamping voltage at CLAMP V(CLP_CLAMP) 0.7 1.1 V IN+ = High, IN- = Low, I(CLP) = 20 mA 10
Blanking capacitor charge current I(CHG) 0.42 0.5 0.58 mA V(DESAT) - GND2 = 2 V 10
DESAT threshold voltage with respect to GND2 V(DSTH) 8.3 9 9.5 V 10
DESAT voltage with respect to GND2, when OUT is driven low V(DSL) 0.4 1 V 10
Output signal rise time tr 12 20 35 ns CLOAD = 1 nF 11
Output signal fall time tf 12 20 37 ns CLOAD = 1 nF 11
Propagation Delay tPLH, tPHL 76 110 ns CLOAD = 1 nF 11
Pulse Skew /tPHL, tPLH/ tsk-p 20 ns 11
Part-to-part skew tsk-pp 30 ns Measured at same supply voltage and temperature condition 11
Glitch filter on IN+, IN-, RST tGF 20 30 40 ns 11
DESAT sense to 10% OUT delay tDESAT (10%) 300 415 500 ns 11
DESAT sense to FLT-low delay tDESAT (FLT) 2000 2420 ns see 图 8-3 11
Leading edge blanking time tLEB 330 400 500 ns see 图 8-1 and 图 8-2 11
Input capacitance CI 2 pF VI = VCC1/2 + 0.4 x sin(2πft), f = 1 MHz, VCC1 = 5 V 11
Common-mode transient immunity CMTI 100 120 kV/μs VCM = 1500 V, see 图 8-4 11

CAD (KiCad official)

  • Symbol: ISO5851DWR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: iso5851dwr-etched.step / iso5851dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); iso5851dwr.step / iso5851dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 2d6206edde371291, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF