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ISO5452DWR

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Texas Instruments Isolators - Gate Drivers, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ISO5452DWR

Texas Instruments · Isolators - Gate Drivers · SOIC-16-300mil

ISO5452DWR from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VEE2 power_in Output negative supply, recommended -15 V to 0 V with respect to GND2; connect to GND2 for unipolar supply application.
2 DESAT input Desaturation voltage input, absolute range GND2 - 0.3 V to VCC2 + 0.3 V.
3 GND2 power_in Gate drive common; connect to the IGBT emitter.
4 OUTH output Positive gate drive voltage output, with 2.5 A pullup capability.
5 VCC2 power_in Most positive output supply potential, recommended 15 V to 30 V with respect to GND2.
6 OUTL output Negative gate drive voltage output, with 5 A pulldown capability.
7 CLAMP output Miller clamp output, sinks Miller current up to 2 A through a low-impedance path when the gate is below 2 V.
8 VEE2 power_in Output negative supply, recommended -15 V to 0 V with respect to GND2; connect to GND2 for unipolar supply application.
9 GND1 power_in Input ground.
10 IN+ input Non-inverting gate drive voltage control input, with VIH of 0.7 × VCC1 to VCC1 and VIL of 0 to 0.3 × VCC1.
11 IN- input Inverting gate drive voltage control input, with VIH of 0.7 × VCC1 to VCC1 and VIL of 0 to 0.3 × VCC1.
12 RDY output Power-good output, high when both supplies are good and low when either side is undervoltage.
13 FLT output Fault output, low-active during a DESAT condition and latched until reset via RST after RDY goes high.
14 RST input Reset input; apply a low pulse of at least 800 ns to reset the fault latch.
15 VCC1 power_in Positive input supply, 2.25 V to 5.5 V.
16 GND1 power_in Input ground.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16-300mil
Category Power Management (PMIC)
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage input side (VCC1, GND1) VCC1 -0.3 6 V 6
Positive supply voltage output side (VCC2, GND2) VCC2 -0.3 35 V 6
Negative supply voltage output side (VEE2, GND2) VEE2 -17.5 0.3 V 6
Total supply output voltage (VCC2, VEE2) V(SUP2) -0.3 35 V 6
Gate driver high output current I(OUTH) 2.7 A maximum pulse width = 10 μs, maximum duty cycle = 0.2% 6
Gate driver low output current I(OUTL) 5.5 A maximum pulse width = 10 μs, maximum duty cycle = 0.2% 6
Voltage at IN+, IN-, FLT, RDY, RST V(LIP) -0.3 V 6
Output current of FLT, RDY I(LOP) 10 mA 6
Voltage at DESAT V(DESAT) -0.3 V 6
Junction temperature TJ -40 150 °C 6
Storage temperature TSTG -65 150 °C 6
Supply voltage input side VCC1 2.25 5.5 V 6
Positive supply voltage output side (VCC2, GND2) VCC2 15 30 V 6
Negative supply voltage output side (VEE2, GND2) VEE2 -15 0 V 6
Total supply voltage output side (VCC2, VEE2) V(SUP2) 15 30 V 6
Low-level input voltage (IN+, IN-, RST) VIL 0 V 6
Pulse width at IN+, IN- for full output tUI 40 ns CLOAD = 1 nF 6
Pulse width at RST for resetting fault latch tRST 800 ns 6
Ambient temperature TA -40 125 °C 6
Common-mode transient immunity CMTI 50 kV/μs VCM = 1500 V 13
Propagation delay tPLH, tPHL 110 ns CLOAD = 1 nF 13
Glitch filter on IN+, IN-, RST tGF 20 40 ns CLOAD = 1 nF 13
Leading edge blanking time tLEB 310 480 ns 13
Output signal rise time tr 12 35 ns CLOAD = 1 nF 13
Output signal fall time tf 12 37 ns CLOAD = 1 nF 13
Blanking capacitor charge current I(CHG) 0.42 0.58 mA V(DESAT), GND2 = 2 V 12
DESAT threshold voltage with respect to GND2 V(DSTH) 8.3 9.5 V 12
Low-level clamp current I(CLP) 1.6 3.3 A V(CLAMP) = VEE2 + 2.5 V 12
Clamp threshold voltage V(CLTH) 1.6 2.5 V 12
Maximum power dissipation PD 1255 mW VCC1 = 5.5 V, VCC2 = 30 V, TA = 25°C 7
Maximum input power dissipation PID 175 mW VCC1 = 5.5 V, VCC2 = 30 V, TA = 25°C 7
Maximum output power dissipation POD 1080 mW VCC1 = 5.5 V, VCC2 = 30 V, TA = 25°C 7
Junction-to-ambient thermal resistance (DW, 16 pins) RθJA 99.6 °C/W 7
Junction-to-case (top) thermal resistance (DW, 16 pins) RθJC(top) 48.5 °C/W 7
Junction-to-board thermal resistance (DW, 16 pins) RθJB 56.5 °C/W 7
Junction-to-top characterization parameter (DW, 16 pins) ψJT 29.2 °C/W 7
Junction-to-board characterization parameter (DW, 16 pins) ψJB 56.5 °C/W 7

CAD (KiCad official)

  • Symbol: ISO5452DWR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: iso5452dwr-etched.step / iso5452dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); iso5452dwr.step / iso5452dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 ddf5480c12c62895, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF