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ISO1640DWR

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TEXAS INSTRUMENTS Global Sourcing Parts, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ISO1640DWR

TEXAS INSTRUMENTS · Global Sourcing Parts · SOIC-16

ISO1640DWR from TEXAS INSTRUMENTS, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND1 power_in Ground for side 1, which is referenced to the local ground for all side 1 voltages.
2 NC unconnected No connection.
3 VCC1 power_in Side 1 supply voltage, 3.0 V to 5.5 V recommended operating range.
4 NC unconnected No connection.
5 SDA1 bidirectional Side 1 serial data input/output, open-drain with 3.5-mA sink capability and 80 pF maximum capacitive load.
6 SCL1 bidirectional Side 1 serial clock input/output (ISO1640), open-drain with 3.5-mA sink capability and 80 pF maximum capacitive load.
7 GND1 power_in Ground for side 1, which is referenced to the local ground for all side 1 voltages.
8 NC unconnected No connection.
9 GND2 power_in Ground for side 2, which is referenced to the local ground for all side 2 voltages.
10 NC unconnected No connection.
11 SCL2 bidirectional Side 2 serial clock input/output (ISO1640), open-drain with 50-mA sink capability and 400 pF maximum capacitive load.
12 SDA2 bidirectional Side 2 serial data input/output, open-drain with 50-mA sink capability and 400 pF maximum capacitive load.
13 NC unconnected No connection.
14 VCC2 power_in Side 2 supply voltage, 2.25 V to 5.5 V recommended operating range.
15 NC unconnected No connection.
16 GND2 power_in Ground for side 2, which is referenced to the local ground for all side 2 voltages.

Key specifications

Parameter Value
Manufacturer TEXAS INSTRUMENTS
Package SOIC-16
Category Global Sourcing Parts
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC1, VCC2 -0.5 6 V 8
I/O voltage SDA1, SCL1 -0.5 V max VCCX + 0.5 8
Input/Output current SDA1, SCL1 0 20 mA 8
Input/Output current SDA2, SCL2 0 100 mA 8
Maximum junction temperature TJ 150 °C 8
Storage temperature Tstg -65 150 °C 8
HBM ESD, all pins V(ESD) -6000 6000 V HBM per ANSI/ESDA/JEDEC JS-001 8
HBM ESD, bus pins SDA1, SCL1 V(ESD) -10000 10000 V ISO1640/1, HBM 8
HBM ESD, bus pins SDA2, SCL2 V(ESD) -14000 14000 V ISO1640/1, HBM 8
CDM ESD V(ESD) -1500 1500 V CDM per JS-002 8
IEC ESD contact discharge across barrier V(ESD) -8000 8000 V IEC 61000-4-2, isolation barrier withstand test 8
Supply voltage, Side 1 VCC1 3 5.5 V 8
Supply voltage, Side 2 VCC2 2.25 5.5 V 8
VCC1 UVLO threshold rising VCC1(UVLO+) 2.7 2.9 V Side 1 supply rising 8
VCC1 UVLO threshold falling VCC1(UVLO-) 2.3 2.6 V Side 1 supply falling 8
VCC2 UVLO threshold rising VCC2(UVLO+) 2 2.25 V Side 2 supply rising 8
VCC2 UVLO threshold falling VCC2(UVLO-) 1.7 1.8 V Side 2 supply falling 8
I2C low-level input voltage, Side 1 VIL1 0 480 mV 9
I2C output current, Side 1 IOL1 0.5 3.5 mA 9
I2C output current, Side 2 IOL2 0.5 50 mA 9
Capacitive load, Side 1 C1 80 pF 9
Capacitive load, Side 2 C2 400 pF 9
I2C operating frequency fMAX 1.7 MHz 9
Ambient temperature TA -40 25 125 °C 9
Junction-to-ambient thermal resistance RθJA 62.4 °C/W DW (SOIC) 16 pins, ISO1640/1 9
Junction-to-case (top) thermal resistance RθJC(top) 29.5 °C/W DW (SOIC) 16 pins, ISO1640/1 9
Junction-to-board thermal resistance RθJB 33.5 °C/W DW (SOIC) 16 pins, ISO1640/1 9
Junction-to-top characterization parameter ψJT 11.7 °C/W DW (SOIC) 16 pins, ISO1640/1 9
Junction-to-board characterization parameter ψJB 32.4 °C/W DW (SOIC) 16 pins, ISO1640/1 9
Maximum power dissipation (both sides) PD 96 mW VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 = 1.4 kΩ, R2 = 94 Ω, 1.7-MHz 50% duty-cycle clock 10
Voltage input threshold low (SDA1, SCL1) VILT1 480 560 mV 14
Voltage input threshold high (SDA1, SCL1) VIHT1 520 620 mV 14
Voltage input hysteresis, Side 1 VHYST1 50 60 mV VIHT1, VILT1 14
Low-level output voltage (SDA1, SCL1) VOL1 570 650 710 mV 0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA 14
Low-level output to high-level input threshold difference ΔVOIT1 50 mV 0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA 14
Low-level output voltage (SDA2, SCL2) VOL2 0.4 V 0.5 mA ≤ (ISDA2 and ISCL2) ≤ 50 mA 14
Input leakage currents /II/ 0.01 10 µA VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2 14
Input capacitance to local ground CI 10 pF VI = 0.4 × sin(2e6*πt) + VDDx / 2 14
Common-mode transient immunity CMTI 50 100 kV/µs VCM = 1000 V 14
Supply current Side 2, SDA/SCL low ICC2 4.9 6.6 mA 2.25 V ≤ VCC2 ≤ 2.75 V, VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2, R1 and R2 = Open, C1 and C2 = Open 15
Supply current Side 2, SDA/SCL high ICC2 2.7 3.5 mA 2.25 V ≤ VCC2 ≤ 2.75 V, VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2, R1 and R2 = Open, C1 and C2 = Open 15
Supply current Side 1, SDA/SCL low ICC1 5.2 7.1 mA 3 V ≤ VCC1, VCC2 ≤ 3.6 V, VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2, R1 and R2 = Open, C1 and C2 = Open 15
Supply current Side 1, SDA/SCL high ICC1 3 4 mA 3 V ≤ VCC1, VCC2 ≤ 3.6 V, VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2, R1 and R2 = Open, C1 and C2 = Open 15
Supply current Side 2, SDA/SCL low ICC2 4.9 6.7 mA 3 V ≤ VCC1, VCC2 ≤ 3.6 V, VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2, R1 and R2 = Open, C1 and C2 = Open 16
Supply current Side 2, SDA/SCL high ICC2 2.8 3.5 mA 3 V ≤ VCC1, VCC2 ≤ 3.6 V, VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2, R1 and R2 = Open, C1 and C2 = Open 16
Supply current Side 1, SDA/SCL low ICC1 5.3 7.2 mA 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V, VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2, R1 and R2 = Open, C1 and C2 = Open 17
Supply current Side 1, SDA/SCL high ICC1 3 4.1 mA 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V, VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2, R1 and R2 = Open, C1 and C2 = Open 17
Supply current Side 2, SDA/SCL low ICC2 5 6.8 mA 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V, VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2, R1 and R2 = Open, C1 and C2 = Open 18
Supply current Side 2, SDA/SCL high ICC2 2.8 3.6 mA 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V, VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2, R1 and R2 = Open, C1 and C2 = Open 18
Time to recover from UVLO tUVLO 36 95 151 µs VCC1 > VCC1(UVLO+) or VCC2 > VCC2(UVLO+), I2C bus Idle 18
Output fall time SDA1/SCL1 (70%-30%) tf1 8 17 29 ns 3 V ≤ VCC1, VCC2 ≤ 3.6 V, 0.7 × VCC1 ≥ VO ≥ 0.3 × VCC1, R1 = 953 Ω, C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF 19
Output fall time SDA2/SCL2 (70%-30%) tf2 14 23 47 ns 3 V ≤ VCC1, VCC2 ≤ 3.6 V, 0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 95.3 Ω, C2 = 400 pF 19
Round-trip propagation delay on side 1 tLOOP1 65 78 ns 3 V ≤ VCC1, VCC2 ≤ 3.6 V, 0.4 V ≤ VI ≤ 0.3 × VCC1, R1 = 953 Ω, C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF 19
Output fall time SDA1/SCL1 (70%-30%) tf1 6 16 22 ns 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V, 0.7 × VCC1 ≥ VO ≥ 0.3 × VCC1, R1 = 1430 Ω, C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF 20
Output fall time SDA2/SCL2 (70%-30%) tf2 10 24 30 ns 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V, 0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 143 Ω, C2 = 400 pF 20
Round-trip propagation delay on side 1 tLOOP1 84 96 ns 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V, 0.4 V ≤ VI ≤ 0.3 × VCCI, R1 = 1430 Ω, C1 = 40 pF, R2 = 143 Ω, C2 = 400 pF 20

CAD (KiCad official)

  • Symbol: ISO1640DWR
  • Footprint: Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: iso1640dwr-etched.step / iso1640dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); iso1640dwr.step / iso1640dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TEXAS INSTRUMENTS datasheet (58 pp, sha256 5dc75560d1771a01, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF