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ISL95808HRZ-T

Public Made by Adom

by adom

RENESAS Gate Drive ICs, DFN-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ISL95808HRZ-T

RENESAS · Gate Drive ICs · DFN-8-EP(2x2)

ISL95808HRZ-T from RENESAS, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 UGATE output Upper gate drive output that connects to the gate of the high-side power N-Channel MOSFET.
2 BOOT power_in Floating bootstrap supply pin for the upper gate drive, with the bootstrap capacitor connected between this pin and PHASE to provide the charge to turn on the upper MOSFET.
3 PWM input Three-state control input for the driver that connects to the PWM output of the controller.
4 GND power_in Ground pin for the IC.
5 LGATE output Lower gate drive output that connects to the gate of the low-side power N-Channel MOSFET.
6 VCC power_in Connects to a +5V bias supply (5V ±10%) with a high quality bypass capacitor to GND, sharing a common +5V supply with the controller's VCC pin.
7 FCCM input Enables diode emulation when LOW, forces continuous conduction mode when HIGH, and high impedance on this input shuts down the ISL95808.
8 PHASE passive Connects to the source of the upper MOSFET and the drain of the lower MOSFET and provides a return path for the upper gate driver.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer RENESAS
Package DFN-8-EP(2x2)
Category Power Management ICs
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Shutdown Bias Supply Current IVCCSD 3.3 4 µA PWM and FCCM pin floating 3
POR Rising Threshold 3.4 3.9 V VCC Rising 3
POR Falling Threshold (HRZ) 2.4 2.9 V VCC Falling 3
Bootstrap Diode Forward Voltage (HRZ) 0.43 0.55 0.65 V VVCC = 5V, forward bias current = 2mA 3
PWM Three-State Rising Threshold 0.7 1 1.3 V VVCC = 5V 3
PWM Three-State Falling Threshold 3.5 3.8 4.1 V VVCC = 5V 3
Three-State Shutdown Hold-Off Time (HRZ) 100 175 250 ns VVCC = 5V, temperature = +25°C 3
FCCM Shutdown Rising Threshold 1.4 1.8 2.2 V VVCC = 5V 3
FCCM Shutdown Falling Threshold 2.8 3.2 3.6 V VVCC = 5V 4
PS4 Exit Latency tPS4EXIT 15 µs VVCC = 5V 4
Upper Drive Source Resistance RU 1 2.5 Ω 500mA source current 4
Upper Drive Sink Resistance RU 1 2.5 Ω 500mA sink current 4
Lower Drive Source Resistance RL 1 2.5 Ω 500mA source current 4
Lower Drive Sink Resistance RL 0.5 1 Ω 500mA sink current 4
Operating Bias Supply Current IVCC 80 µA PWM pin floating, VFCCM = 5V 3
Operating Bias Supply Current IVCC 120 µA PWM pin floating, VFCCM = 0V 3
POR Hysteresis 500 mV 3
PWM Input Current IPWM 250 µA VPWM = 5V 3
PWM Input Current IPWM -250 µA VPWM = 0V 3
FCCM Input Current IFCCM 50 µA VFCCM = 5V 3
UGATE Rise Time tRU 8 ns VVCC = 5V, 3nF load 4
LGATE Rise Time tRL 8 ns VVCC = 5V, 3nF load 4
UGATE Fall Time tFU 8 ns VVCC = 5V, 3nF load 4
LGATE Fall Time tFL 4 ns VVCC = 5V, 3nF load 4
UGATE Turn-Off Propagation Delay tPDLU 18 ns VVCC = 5V, outputs unloaded 4
LGATE Turn-Off Propagation Delay tPDLL 25 ns VVCC = 5V, outputs unloaded 4
UGATE Turn-On Propagation Delay tPDHU 20 ns VVCC = 5V, outputs unloaded 4
LGATE Turn-On Propagation Delay tPDHL 20 ns VVCC = 5V, outputs unloaded 4
UG/LG Three-State Propagation Delay tPTS 35 ns VVCC = 5V, outputs unloaded 4
Minimum LG On-Time in DCM tLGMIN 350 ns 4
Upper Driver Source Current IU 2 A VUGATE-PHASE = 2.5V 4
Upper Driver Sink Current IU 2 A VUGATE-PHASE = 2.5V 4
Lower Driver Source Current IL 2 A VLGATE = 2.5V 4
Lower Driver Sink Current IL 4 A VLGATE = 2.5V 4
Supply Voltage VCC -0.3 7 V 3
BOOT Voltage (VBOOT-GND) -0.3 33 V 36V (<20ns) 3
BOOT To PHASE Voltage VBOOT-PHASE -0.3 7 V DC; -0.3V to 9V (<10ns) 3
PHASE Voltage -0.3 30 V (GND - 0.3V) to 30V; GND - 8V (<20ns Pulse Width, 10µJ) 3
Maximum Storage Temperature -65 150 °C 3
Ambient Temperature (HRZ) TA -10 100 °C HRZ 3
Maximum Operating Junction Temperature TJ 125 °C 3
Thermal Resistance Junction-Ambient θJA 87 °C/W 8 Ld 2x2 DFN, free air, Notes 5, 6 3
Thermal Resistance Junction-Case θJC 22 °C/W 8 Ld 2x2 DFN, Notes 5, 6 3

CAD (KiCad official)

  • Symbol: ISL95808HRZ-T
  • Footprint: Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm
  • 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: isl95808hrz-t-etched.step / isl95808hrz-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isl95808hrz-t.step / isl95808hrz-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (9 pp, sha256 0639f908d1ba632b, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF