# ISL9113AIRAZ-T

**RENESAS** · DC-DC Converters · DFN-8-EP(2x2)

ISL9113AIRAZ-T from RENESAS, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Power ground for the converter; the exposed pad must be connected to this pin. |
| 2 | VOUT | power_out | Device output, with recommended operating range (VBAT + 0.2V) to 5.2V and an output overvoltage protection threshold of 5.9V. |
| 3 | NC | unconnected | No connection. |
| 4 | FB | input | Feedback pin of the converter; voltage divider resistors connect between VOUT, FB and GND, with a feedback voltage of 784 to 816 mV and input current of 100 nA maximum at VFB = 0.8V. |
| 5 | EN | input | Active-HIGH enable input; logic high is 1.2V minimum for 2.5V < VBAT < 4.7V and logic low is 0.35V maximum in that range. |
| 6 | AGND | power_in | Analog ground. |
| 7 | VBAT | power_in | Device input supply from a battery, with recommended range 0.8V to 4.7V after start-up; connect a 4.7µF ceramic capacitor to power ground. |
| 8 | SW | passive | Switching node of the power converter; connect one terminal of the 2.2µH inductor to SW and the other to the power input. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | DFN-8-EP(2x2) |
| Category | Power Management ICs |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Start-Up Voltage | VMIN | 0.75 |  | 0.9 | V | VEN = VBAT, RLOAD = 50Ω | 4 |
| Input Undervoltage Lockout | VUVLO | 0.66 | 0.7 | 0.76 | V | VEN = VBAT, RLOAD = 50Ω | 4 |
| Feedback Voltage | VFB | 784 | 800 | 816 | mV |  | 4 |
| Output Voltage | VOUT | 3 |  | 5.2 | V | VBAT = 2.8V | 4 |
| Feedback Pin Input Current | IFB |  |  | 100 | nA | VFB = 0.8V | 4 |
| Quiescent Current from VOUT | IQ1 |  | 20 | 45 | μA | VBAT = VEN = 1.2V, no load (Note 7) | 4 |
| Shutdown Current from VBAT | ISD |  | 0.5 | 2.8 | μA | VEN = 0V, VBAT = 1.2V, VO = 0 | 4 |
| Leakage Current at SW Pin |  |  |  | 1 | μA | VEN = 0V, VBAT = 4.7V, VO = 0 | 4 |
| N-Channel MOSFET Peak Current Limit | IPK | 1.1 | 1.3 | 1.5 | A |  | 4 |
| Maximum Duty Cycle | DMAX | 82 |  | 87.5 | % |  | 4 |
| PWM Switching Frequency | FOSC | 1.5 | 1.8 | 2 | MHz |  | 4 |
| EN Logic High |  | 1.2 |  |  | V | 2.5V < VBAT < 4.7V | 4 |
| EN Logic Low |  |  |  | 0.35 | V | 2.5V < VBAT < 4.7V | 4 |
| Soft Start-Up Time |  |  | 0.2 | 1 | ms | COUT = 4.7μF, L = 2.2μH | 4 |
| Load Regulation | ΔVOUT/VOUT | -1.5 |  | 1.5 | % | ILOAD = 0 to 50mA | 4 |
| Line Regulation |  | -1 |  | 1 | % | VBAT = 3.0V to 3.6V, ILOAD = 1mA | 4 |
| Output Overvoltage Protection Threshold |  |  |  | 5.9 | V |  | 4 |
| Thermal Shutdown | TSD |  | 150 |  | oC |  | 4 |
| Thermal Shutdown Hysteresis |  |  | 25 |  | oC |  | 4 |
| N-Channel MOSFET ON-Resistance | RDS(ON) |  | 0.2 |  | Ω |  | 4 |
| P-Channel MOSFET ON-Resistance | RDS(ON) |  | 0.35 |  | Ω |  | 4 |
| VBAT, EN, VOUT voltage |  | -0.3 |  | 6.5 | V |  | 4 |
| SW Voltage DC |  | -0.5 |  | 6.5 | V | DC | 4 |
| SW Voltage Pulse |  | -0.5 |  | 8 | V | Pulse <10ns | 4 |
| ESD Human Body Model |  |  |  | 3 | kV | Human Body Model (Tested per JESD22-A114F) | 4 |
| Latch-Up |  |  |  | 100 | mA | Tested per JESD78; Class 2, Level A | 4 |
| Junction Temperature Range | TJ | -40 |  | 125 | °C |  | 4 |
| Storage Temperature Range | TSTG | -65 |  | 150 | °C |  | 4 |
| VBAT (After start-up) | VBAT | 0.8 |  | 4.7 | V | After start-up | 4 |
| VOUT (recommended maximum) | VOUT |  |  | 5.2 | V |  | 4 |
| Ambient Temperature Range | TA | -40 |  | 85 | °C |  | 4 |
| Operating Temperature Range |  | -40 |  | 85 | °C |  | 4 |
| Thermal Resistance Junction-to-Ambient 8 Ld DFN | θJA |  | 80 |  | °C/W | Free air, high-effective thermal conductivity test board (Notes 4, 5) | 4 |
| Thermal Resistance Junction-to-Case 8 Ld DFN | θJC |  | 15 |  | °C/W | Case temp at center of exposed metal pad (Note 5) | 4 |

## CAD (KiCad official)

- Symbol: `ISL9113AIRAZ-T`
- Footprint: `Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm`
- 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files: `isl9113airaz-t-etched.step` / `isl9113airaz-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `isl9113airaz-t.step` / `isl9113airaz-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [RENESAS datasheet](docs/isl9113airaz-t-datasheet.pdf) (10 pp, sha256 `2b81afa1457b0754`, retrieved 2026-11-02, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/isl9113airaz-t-datasheet.pdf)