# ISL854102FRZ-T

**RENESAS** · DC-DC Converters · DFN-12-EP(3x4)

ISL854102FRZ-T from RENESAS, in a DFN-12-EP(3x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SS | input | Sets the soft-start ramp time via a single capacitor to ground; if tied to VCC an internal 2ms soft-start is used. |
| 2 | SYNC | input | Synchronization and light-load mode select: high or VCC for PWM, low or ground for automatic PFM/PWM, or an external clock (positive edge) higher than the programmed frequency; internal 5MΩ pull-down. |
| 3 | BOOT | passive | Floating bootstrap supply for the power MOSFET gate driver; connect a 100nF capacitor from this pin to PHASE. |
| 4 | VIN | power_in | Input supply for the regulator power stage and internal linear bias regulator; place at least 4.7µF ceramic capacitance from VIN to GND close to the IC. |
| 5 | PHASE | output | Switch node output connecting the switching FETs to the external output inductor. |
| 6 | PGND | power_in | Power ground connection, connected directly to the system GND plane. |
| 7 | EN | input | Regulator enable input; the regulator and bias LDO are off when pulled to ground and enabled when the pin rises above 1V; connect to VIN for automatic start-up and do not connect to VCC. |
| 8 | PG | output | Open-drain power-good output pulled to ground when the output is below regulation limits or during soft-start, with an internal 5MΩ pull-up resistor. |
| 9 | VCC | power_out | Output of the internal 5V linear bias regulator; decouple to PGND with a 1µF ceramic capacitor. |
| 10 | FB | input | Feedback input to the voltage loop error amplifier, set by an external resistor divider and also monitored by the power-good and UVLO circuits. |
| 11 | COMP | passive | Error amplifier output; tie to VCC for internal compensation, or connect an RC network to GND for external compensation. |
| 12 | FS | input | Frequency selection pin; tie to VCC for 500kHz or connect a resistor to GND for adjustable 300kHz to 2MHz. |
| 13 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | DFN-12-EP(3x4) |
| Category | Power Management ICs |
| Pins | 13 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Voltage Range | VIN | 3 |  | 40 | V |  | 7 |
| VIN Quiescent Supply Current | IQ |  | 80 |  | µA | VFB = 0.7V, SYNC = 0V, fSW = VCC | 7 |
| VIN Shutdown Supply Current | ISD |  | 2 | 4 | µA | EN = 0V, VIN = 40V (Note 7) | 7 |
| VCC Voltage | VCC | 4.5 | 5.1 | 5.7 | V | VIN = 6V, IOUT = 0 to 10mA | 7 |
| VCC POR Threshold Rising |  |  | 2.75 | 2.95 | V | Rising edge | 7 |
| VCC POR Threshold Falling |  | 2.35 |  | 2.6 | V | Falling edge | 7 |
| Nominal Switching Frequency (FS = VCC) | fSW | 430 | 500 | 570 | kHz | FS pin = VCC | 7 |
| Nominal Switching Frequency (340kΩ) | fSW | 240 | 300 | 360 | kHz | Resistor from the FS pin to GND = 340kΩ | 7 |
| Nominal Switching Frequency (32.4kΩ) | fSW |  | 2000 |  | kHz | Resistor from the FS pin to GND = 32.4kΩ | 7 |
| FB Voltage (-40 to +85°C) |  | 0.59 | 0.599 | 0.606 | V | TA = -40°C to +85°C | 7 |
| FB Voltage (-40 to +125°C) |  | 0.59 | 0.599 | 0.607 | V | TA = -40°C to +125°C | 7 |
| Error Amplifier Transconductance Gain, external compensation | gm | 165 | 230 | 295 | µA/V | External compensation | 7 |
| Current Sense Amplifier Gain | RT | 0.46 | 0.5 | 0.54 | V/A |  | 7 |
| Lower PG Threshold - VFB Rising |  | 90 |  | 94 | % |  | 8 |
| Lower PG Threshold - VFB Falling |  | 82.5 |  | 86 | % |  | 8 |
| Upper PG Threshold - VFB Rising |  | 116.5 |  | 120 | % |  | 8 |
| Upper PG Threshold - VFB Falling |  | 107 |  | 112 | % |  | 8 |
| PG Low Voltage |  |  | 0.05 | 0.3 | V | ISINK = 3mA, EN = VCC, VFB = 0V | 8 |
| Soft-Start Charging Current | ISS | 4.2 | 5.5 | 6.5 | µA |  | 8 |
| Internal Soft-Start Ramp Time |  | 1.5 | 2.4 | 3.4 | ms | EN/SS = VCC | 8 |
| Positive Peak Current Limit | IPLIMIT | 1.4 | 1.6 | 1.8 | A | (Note 8) | 8 |
| PFM Peak Current Limit | IPK_PFM | 0.34 | 0.4 | 0.5 | A |  | 8 |
| Negative Current Limit | INLIMIT | -0.67 | -0.6 | -0.53 | A | (Note 8) | 8 |
| High-Side RDS(on) | RHDS |  | 250 | 350 | mΩ | IPHASE = 100mA, VCC = 5V | 8 |
| Low-Side RDS(on) | RLDS |  | 90 | 130 | mΩ | IPHASE = 100mA, VCC = 5V | 8 |
| Input Threshold Rising edge, logic high |  | 1.2 |  | 1.4 | V | Rising edge, logic high | 8 |
| EN Logic Input Leakage Current |  | -0.5 |  | 0.5 | µA | EN = 0V/40V | 8 |
| Error Amplifier Transconductance Gain, internal compensation | gm |  | 50 |  | µA/V | Internal compensation | 7 |
| Minimum Off-Time | tMIN_OFF |  |  | 150 | ns | VIN = 3V | 7 |
| Minimum On-Time | tMIN_ON |  |  | 90 | ns | (Note 10) | 7 |
| FS Voltage | VFS | 0.39 | 0.4 | 0.41 | V | RFS = 100kΩ | 7 |
| Synchronization Frequency | SYNC | 300 |  | 2000 | kHz |  | 7 |
| Thermal Shutdown Temperature | TSD |  | 150 |  | °C | Rising threshold | 8 |
| Thermal Shutdown Hysteresis | THYS |  | 20 |  | °C |  | 8 |
| VIN to GND |  | -0.3 |  | 43 | V |  | 7 |
| PHASE to GND (DC) |  | -0.3 |  |  | V | DC, max is VIN + 0.3V | 7 |
| PHASE to GND (20ns) |  | -2 |  | 44 | V | 20ns | 7 |
| EN to GND |  | -0.3 |  | 43 | V |  | 7 |
| BOOT to PHASE |  | -0.3 |  | 5.5 | V |  | 7 |
| COMP, FS, PG, SYNC, SS, VCC to GND |  | -0.3 |  | 5.9 | V |  | 7 |
| FB to GND |  | -0.3 |  | 2.95 | V |  | 7 |
| Maximum Junction Temperature |  |  |  | 150 | °C | Plastic package | 7 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 7 |
| Ambient Temperature Range |  | -40 |  | 125 | °C |  | 7 |
| ESD Human Body Model |  |  |  | 2 | kV | JESD22-A114 | 7 |
| ESD Charged Device Model |  |  |  | 1.5 | kV | JESD22-C101E | 7 |
| Junction Temperature |  | -40 |  | 125 | °C |  | 7 |
| Supply Voltage |  | 3 |  | 40 | V |  | 7 |
| Thermal Resistance Junction-Ambient | θJA |  | 42 |  | °C/W | DFN package (Notes 5, 6) | 7 |
| Thermal Resistance Junction-Case | θJC |  | 4.5 |  | °C/W | DFN package (Notes 5, 6) | 7 |

## CAD (KiCad official)

- Symbol: `ISL854102FRZ-T`
- Footprint: `Package_DFN_QFN:DFN-12-1EP_3x4mm_P0.5mm_EP1.7x3.3mm`
- 3D model: DFN-12-EP(3x4) (KiCad packages3D, STEP)
- 3D model files: `isl854102frz-t-etched.step` / `isl854102frz-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `isl854102frz-t.step` / `isl854102frz-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [RENESAS datasheet](docs/isl854102frz-t-datasheet.pdf) (21 pp, sha256 `ed0920a189e91349`, retrieved 2026-10-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/isl854102frz-t-datasheet.pdf)