# ISL83202IBZT

**RENESAS** · Pre-ordered Chips · SOIC-16

ISL83202IBZT from RENESAS, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BHB | power_in | B high-side bootstrap supply; connect cathode of external bootstrap diode and positive side of bootstrap capacitor here. |
| 2 | BHI | input | B high-side logic input controlling BHO; overridden by BLI high and by DIS high, driven with 0V to 15V (no greater than VDD). |
| 3 | BLI | input | B low-side logic input controlling BLO; overridden by DIS high, driven with 0V to 15V (no greater than VDD). |
| 4 | ALI | input | A low-side logic input controlling ALO; overridden by DIS high, driven with 0V to 15V (no greater than VDD). |
| 5 | DEL | passive | Turn-on delay pin; connect a resistor to VSS to set the dead time between drivers, with approximately VDD-2V across the resistor. |
| 6 | VSS | power_in | Chip negative supply, generally ground. |
| 7 | AHI | input | A high-side logic input controlling AHO; overridden by ALI high and by DIS high, driven with 0V to 15V (no greater than VDD). |
| 8 | DIS | input | Disable input; high sets all four outputs low and overrides all other inputs, driven with 0V to 15V (no greater than VDD). |
| 9 | AHB | power_in | A high-side bootstrap supply; connect cathode of external bootstrap diode and positive side of bootstrap capacitor here. |
| 10 | AHO | output | A high-side output; connect to gate of A high-side power MOSFET. |
| 11 | AHS | passive | A high-side source connection; connect to source of A high-side MOSFET and negative side of bootstrap capacitor. |
| 12 | VDD | power_in | Positive supply to control logic and lower gate drivers (8.5V to 15V operating); decouple to VSS (pin 6). |
| 13 | ALO | output | A low-side output; connect to gate of A low-side power MOSFET. |
| 14 | BLO | output | B low-side output; connect to gate of B low-side power MOSFET. |
| 15 | BHS | passive | B high-side source connection; connect to source of B high-side MOSFET and negative side of bootstrap capacitor. |
| 16 | BHO | output | B high-side output; connect to gate of B high-side power MOSFET. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | SOIC-16 |
| Category | Interface ICs |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | -0.3 |  | 16 | V | relative to VSS | 4 |
| Logic I/O Voltages |  | -0.3 |  | 0.3 | V | -0.3V to VDD +0.3V (max is VDD+0.3V) | 4 |
| Voltage on AHS, BHS |  | -6 |  | 65 | V | -6V transient; -55°C to +150°C | 4 |
| Input Current, DEL |  | -5 |  | 0 | mA |  | 4 |
| Phase Slew Rate |  |  |  | 20 | V/ns |  | 4 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 4 |
| Operating Max. Junction Temperature | TJ |  |  | 150 | °C |  | 4 |
| Lead Temperature (Soldering 10s) |  |  |  | 300 | °C | SOIC lead tips only | 4 |
| Supply Voltage | VDD | 8.5 |  | 15 | V |  | 4 |
| Voltage on VSS | VSS | -1 |  | 1 | V |  | 4 |
| Voltage on AHB, BHB |  | -1 |  | 55 | V |  | 4 |
| Thermal Resistance SOIC | θJA |  | 115 |  | °C/W | SOIC package | 4 |
| VDD Quiescent Current | IDD | 1.2 | 2.3 | 3.5 | mA | All inputs = 0V, RDEL = 100k; TJ=+25°C | 4 |
| VDD Quiescent Current | IDD | 2.2 | 4 | 5.5 | mA | All inputs = 0V, RDEL = 10k; TJ=+25°C | 4 |
| VDD Operating Current | IDDO | 1.5 | 2.6 | 4 | mA | f = 50kHz, no load; TJ=+25°C | 4 |
| AHB, BHB Off Quiescent Current | IAHBL, IBHBL | 0.5 | 1 | 1.5 | mA | AHI = BHI = 0V; TJ=+25°C | 4 |
| AHB, BHB On Quiescent Current | IAHBH, IBHBH | 65 | 145 | 240 | µA | AHI = BHI = VDD; TJ=+25°C | 4 |
| AHB, BHB Operating Current | IAHBO, IBHBO | 0.65 | 1.1 | 1.8 | mA | f = 50kHz, CL = 1000pF; TJ=+25°C | 4 |
| AHS, BHS Leakage Current | IHLK |  |  | 1 | µA | VAHS = VBHS = 55V, VAHB = VBHB = 70V, VDD = Not Connected | 4 |
| VDD Rising Undervoltage Threshold | VDDUV+ | 6.8 | 7.6 | 8.25 | V | TJ=+25°C | 4 |
| VDD Falling Undervoltage Threshold | VDDUV- | 6.5 | 7.1 | 7.8 | V | TJ=+25°C | 4 |
| Undervoltage Hysteresis | UVHYS | 0.17 | 0.4 | 0.75 | V | TJ=+25°C | 4 |
| AHB, BHB Undervoltage Threshold | VHBUV | 5 | 6 | 7 | V | Referenced to AHS and BHS; TJ=+25°C | 4 |
| Low Level Input Voltage | VIL |  |  | 1 | V | Full Operating Conditions; TJ=+25°C | 4 |
| High Level Input Voltage | VIH | 2.5 |  |  | V | Full Operating Conditions; TJ=+25°C | 4 |
| Low Level Input Current | IIL | -145 | -100 | -60 | µA | VIN = 0V, Full Operating Conditions; TJ=+25°C | 4 |
| High Level Input Current | IIH | -1 |  | 1 | µA | VIN = 5V, Full Operating Conditions; TJ=+25°C | 4 |
| Dead Time | TDEAD | 2.5 | 4.5 | 8 | µs | RDEL = 100k; TJ=+25°C | 4 |
| Dead Time | TDEAD | 0.27 | 0.5 | 0.75 | µs | RDEL = 10k; TJ=+25°C | 4 |
| Low Level Output Voltage | VOL |  | 0.65 | 1.1 | V | IOUT = 50mA; TJ=+25°C | 5 |
| High Level Output Voltage | VDD-VOH |  | 0.7 | 1.2 | V | IOUT = -50mA; TJ=+25°C | 5 |
| Peak Pullup Current | IO+ |  | 1 |  | A | VOUT = 0V; TJ=+25°C | 5 |
| Peak Pulldown Current | IO- |  | 1 |  | A | VOUT = 12V; TJ=+25°C | 5 |
| Lower Turn-off Propagation Delay | TLPHL |  | 25 | 50 | ns | ALI-ALO, BLI-BLO; TJ=+25°C | 5 |
| Upper Turn-off Propagation Delay | THPHL |  | 55 | 80 | ns | AHI-AHO, BHI-BHO; TJ=+25°C | 5 |
| Lower Turn-on Propagation Delay | TLPLH |  | 40 | 85 | ns | ALI-ALO, BLI-BLO; TJ=+25°C | 5 |
| Upper Turn-on Propagation Delay | THPLH |  | 75 | 110 | ns | AHI-AHO, BHI-BHO; TJ=+25°C | 5 |
| Rise Time | TR |  | 9 | 20 | ns | TJ=+25°C | 5 |
| Fall Time | TF |  | 9 | 20 | ns | TJ=+25°C | 5 |
| Minimum Input Pulse Width | TPWIN-ON/OFF | 50 |  |  | ns | TJ=+25°C | 5 |
| Disable Turn-off Propagation Delay (DIS - Lower Outputs) | TDISLOW |  | 50 | 80 | ns | TJ=+25°C | 5 |
| Disable Turn-off Propagation Delay (DIS - Upper Outputs) | TDISHIGH |  | 75 | 100 | ns | TJ=+25°C | 5 |
| Disable Turn-on Propagation Delay (DIS - ALO and BLO) | TDLPLH |  | 40 | 70 | ns | TJ=+25°C | 5 |
| Disable Turn-on Propagation Delay (DIS- AHO and BHO) | TDHPLH |  | 1.2 | 2 | µs | RDEL = 10k; TJ=+25°C | 5 |
| Refresh Pulse Width (ALO and BLO) | TREF-PW | 375 | 580 | 900 | ns | TJ=+25°C | 5 |

## CAD (KiCad official)

- Symbol: `ISL83202IBZT`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `isl83202ibzt-etched.step` / `isl83202ibzt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `isl83202ibzt.step` / `isl83202ibzt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [RENESAS datasheet](docs/isl83202ibzt-datasheet.pdf) (12 pp, sha256 `c390ca83224ac598`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/isl83202ibzt-datasheet.pdf)