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ISL8018IRAJZ-T7A

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RENESAS DC-DC Converters, QFN-20-EP(3x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ISL8018IRAJZ-T7A

RENESAS · DC-DC Converters · QFN-20-EP(3x4)

ISL8018IRAJZ-T7A from RENESAS, in a QFN-20-EP(3x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PGND power_in Power ground; one of three PGND pins (1, 19, 20) on the power ground return.
2 PHASE output Switching node connection; connect to one terminal of the inductor (PHASE pins 2, 3, 4 are tied together).
3 PHASE output Switching node connection; connect to one terminal of the inductor (PHASE pins 2, 3, 4 are tied together).
4 PHASE output Switching node connection; connect to one terminal of the inductor (PHASE pins 2, 3, 4 are tied together).
5 VIN power_in Input supply voltage, 2.7V to 5.5V per the datasheet; connect two 22µF ceramic capacitors to power ground.
6 VIN power_in Input supply voltage, 2.7V to 5.5V per the datasheet; connect two 22µF ceramic capacitors to power ground.
7 VIN power_in Input supply voltage, 2.7V to 5.5V per the datasheet; connect two 22µF ceramic capacitors to power ground.
8 PG output Open-drain power-good output requiring a 10kΩ to 100kΩ pull-up between VIN and PG; PG rising edge is delayed 1ms after the output reaches regulation at power-up or EN high.
9 SYNCOUT output Outputs a 250µA current source turned on at the internal clock or SYNCIN rising edge; reset discharges it to 0V at 0.8V and it is held at 0V in PFM light load.
10 SYNCIN input Mode select (high or VIN for PWM, low or ground for PFM) and positive-edge external synchronization input, with an internal 1MΩ pull-down.
11 EN input Regulator enable; driving high enables the output, driving low shuts down the chip and discharges the output capacitor.
12 FS passive Oscillator frequency set by resistor RFS from FS to GND, programmable 500kHz to 4MHz; default 1MHz with internal compensation when FS is tied to VIN.
13 VSET input Output margining setting: connect to SGND for -10%, leave floating for no margining, connect to VIN for +10%.
14 ISET input Peak and skip current limit setting: connect to SGND for 3A, to VIN for 5A, leave floating for 8A.
15 SS passive Soft-start time adjust: SGND gives internal 1ms rise time; a capacitor from SS to SGND sets longer time, not exceeding 33nF per IC.
16 COMP passive Output of the transconductance error amplifier when the FS resistor is used; tie to SGND when internal compensation is used (FS = VIN).
17 VFB input Negative input to the transconductance error amplifier; set output via external divider to any voltage between VIN and the 0.6V reference, and also used to determine PG state.
18 SGND power_in Signal ground; the exposed pad must be connected to this pin.
19 PGND power_in Power ground; one of three PGND pins (1, 19, 20).
20 PGND power_in Power ground; one of three PGND pins (1, 19, 20).
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer RENESAS
Package QFN-20-EP(3x4)
Category Power Supply Chip
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN Supply Voltage (DC) VIN -0.3 5.8 V DC 6
VIN Supply Voltage (20ms) VIN 7 V 20ms 6
EN, FS, ISET, PG, SYNCOUT, SYNCIN, VFB, VSET Voltage -0.3 V Reference to GND; upper limit VIN + 0.3V 6
PHASE Voltage -1.5 V 100ns 6
PHASE Voltage -0.3 V DC 6
PHASE Voltage 6.5 V DC 6
PHASE Voltage 7 V 20ms 6
COMP, SS Voltage -0.3 2.7 V 6
ESD Human Body Model 3 kV Tested per JESD22-A114 6
ESD Machine Model 300 V Tested per JESD22-A115 6
ESD Charged Device Model 1.5 V Tested per JESD22-C101E 6
Latch-up 100 mA Tested per JESD-78A; Class 2, Level A; at +85°C 6
Junction Temperature Range TJ -55 125 °C 6
Storage Temperature Range TSTG -65 150 °C 6
VIN Supply Voltage Range VIN 2.7 5.5 V 6
Load Current Range 0 8 A 6
Ambient Temperature Range TA -40 85 °C 6
Thermal Resistance Junction-to-Ambient (3x4 QFN) θJA 42 °C/W Free air, high effective thermal conductivity board with direct attach (Notes 4, 5) 6
Thermal Resistance Junction-to-Case (3x4 QFN) θJC 5 °C/W Case at center of exposed metal pad (Note 5) 6
VIN Undervoltage Lockout Threshold (rising) VUVLO 2.5 2.7 V Rising, no load 6
VIN Undervoltage Lockout Threshold (falling) VUVLO 2.2 2.4 V Falling, no load 6
Quiescent Supply Current IVIN 70 95 µA SYNCIN = GND, no load at the output and no switches switching 6
Quiescent Supply Current (switching) IVIN 8 15 mA SYNCIN = VIN, fSW = 1MHz, no load at the output 6
Shutdown Supply Current ISD 5 9.5 µA SYNCIN = GND, VIN = 5.5V, EN = low 6
Reference Voltage (VSET = VIN) VREF 0.651 0.66 0.669 V VSET = VIN 6
Reference Voltage (VSET = FLOAT) VREF 0.594 0.6 0.606 V VSET = FLOAT 6
Reference Voltage (VSET = SGND) VREF 0.531 0.54 0.549 V VSET = SGND 6
Output Voltage Margining (+) VVFB 9.5 10 10.5 % VSET = VIN, percent of output changed 6
Output Voltage Margining (-) VVFB -10.5 -10 -9.5 % VSET = SGND, percent of output changed 6
Soft-Start Charging Current ISS 1.4 1.8 2.2 µA VSS = 0.1V 6
Positive Peak Current Limit (ISET = FLOAT) IPLIMIT 9.7 12.8 15.8 A ISET = FLOAT 7
Positive Peak Current Limit (ISET = VIN) IPLIMIT 6.7 8.8 10.9 A ISET = VIN 7
Positive Peak Current Limit (ISET = SGND) IPLIMIT 4 5.6 7.2 A ISET = SGND 7
Peak Skip Limit (ISET = FLOAT) ISKIP 2.18 2.8 3.78 A ISET = FLOAT 7
Peak Skip Limit (ISET = VIN) ISKIP 1.08 1.66 2.3 A ISET = VIN 7
Zero Cross Threshold -300 300 mA 7
Negative Current Limit INLIMIT -4.25 -3 -1.75 A 7
P-Channel MOSFET ON-Resistance 31 45 mΩ VIN = 5V, IO = 200mA 7
P-Channel MOSFET ON-Resistance 44 55 mΩ VIN = 2.7V, IO = 200mA 7
N-Channel MOSFET ON-Resistance 19 35 mΩ VIN = 5V, IO = 200mA 7
N-Channel MOSFET ON-Resistance 25 50 mΩ VIN = 2.7V, IO = 200mA 7
Nominal Switching Frequency fSW 800 1000 1200 kHz FS = VIN 7
Nominal Switching Frequency (FS with resistor) fSW 440 520 600 kHz FS with RS = 402kΩ 7
Nominal Switching Frequency (FS with resistor) fSW 3200 3700 4200 kHz FS with RS = 42.4kΩ 7
SYNCIN Logic Low to High Transition Range 0.7 0.75 0.8 V 7
SYNCOUT Charging Current ISO 210 250 290 µA PWM 7
PG Delay Time (Rising Edge) 0.5 1 2 ms 7
PG Pin Leakage Current 0.01 0.1 µA 7
UVP PG Rising Threshold 80 85 90 % 7
ISET, VSET Logic Input Float 0.5 0.8 V 8
ISET, VSET Logic Input Leakage Current 0.1 1 µA 8
EN Logic Input Leakage Current 0.1 1 µA 8

CAD (KiCad official)

  • Symbol: ISL8018IRAJZ-T7A
  • Footprint: Package_DFN_QFN:QFN-20-1EP_3x4mm_P0.5mm_EP1.65x2.65mm
  • 3D model: QFN-20-EP(3x4) (KiCad packages3D, STEP)
  • 3D model files: isl8018irajz-t7a-etched.step / isl8018irajz-t7a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isl8018irajz-t7a.step / isl8018irajz-t7a.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (21 pp, sha256 0661a8391fc5d7e1, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF