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ISL80112IRAJZ

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RENESAS Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN-10(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ISL80112IRAJZ

RENESAS · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-10(3x3)

ISL80112IRAJZ from RENESAS, in a DFN-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT power_out Output voltage pin with a range of 0.5V to 3.3V.
2 VOUT power_out Output voltage pin with a range of 0.5V to 3.3V.
3 ADJ input ADJ pin for externally setting VOUT through a resistor divider.
4 VBIAS power_in Bias voltage pin for internal control circuits with a range of 2.9V to 5.5V.
5 GND power_in Ground pin.
6 PG output Open-drain power-good flag, logic low when VOUT is not in regulation, with a range of 0V to VBIAS.
7 ENABLE input VIN-independent chip enable, TTL and CMOS compatible, with a range of 0V to VBIAS that must always be at or below VBIAS; tie to VBIAS when unused.
8 NC unconnected No connect.
9 VIN power_in Input supply pin with a range of 0.7V to 3.6V.
10 VIN power_in Input supply pin with a range of 0.7V to 3.6V.
11 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer RENESAS
Package DFN-10(3x3)
Category Power Management (PMIC)
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VBIAS UVLO rising UVLO_BIAS_r 2.3 2.9 V VBIAS rising 4
VBIAS UVLO falling UVLO_BIAS_f 1.55 2.1 2.8 V VBIAS falling 4
DC ADJ pin voltage accuracy VADJ 494 502 510 mV 0.7V<=VIN<=3.6V, ILOAD=0A, 2.9V<=VBIAS<=5.5V, VOUT=VADJ 4
DC input line regulation -0.18 0.02 0.18 % 2.9V<=VIN<=3.6V, VOUT=2.5V 4
DC bias line regulation -0.28 0.06 0.28 % 4.5V<VBIAS<5.5V, VOUT=2.5V 4
DC output load regulation -0.4 -0.04 0.4 % 0A<=ILOAD<=Full Load, VOUT=2.5V 4
Feedback input current 10 80 nA VADJ=0.5V 4
VIN quiescent current IQ (VIN) 8 10 mA VOUT=2.5V 4
Ground pin current in shutdown ISHDN 3 20 uA ENABLE pin=0.2V, TJ=+125C 5
VIN dropout voltage (ISL80112) VDO(VIN) 53 115 mV ILOAD=2A, VOUT=2.5V, VBIAS=4.5V 5
VBIAS dropout voltage (ISL80112) VDO(BIAS) 1.2 1.4 V ILOAD=2A, VOUT=2.5V 5
Enable turn-on threshold (rising) 400 680 850 mV VIN=3.6V, VBIAS=5.5V 5
Enable hysteresis 60 260 330 mV VIN=3.6V, VBIAS=5.5V 5
PG flag falling threshold PGTH 71 82 93 %VOUT VBIAS=5.5V 5
PG flag low voltage 90 130 mV ISINK=500uA 5
PG flag leakage current 11 300 nA PG=5V, VBIAS=5.5V 5
PG flag sink current 7 10 mA 6
Junction temperature range TJ -40 125 C Recommended operating junction temperature 4
VIN relative to GND (ISL80112) VIN 3.6 V Minimum is VOUT + 0.25V 4
Nominal VOUT range VOUT 0.5 3.3 V Nominal output voltage range 4
PG, ENABLE, ADJ, SS relative to GND 0 5.5 V Relative to GND 4
VBIAS relative to GND VBIAS 0 5.5 V Relative to GND 4
VIN relative to GND VIN -0.3 6 V Relative to GND 4
VOUT relative to GND VOUT -0.3 4 V Relative to GND 4
PG, ENABLE, ADJ relative to GND -0.3 6 V Relative to GND, lifetime average duty cycle above 6V of 1% 4
VBIAS relative to GND VBIAS -0.3 6 V Relative to GND 4
PG rated current 10 mA 4
ESD human body model 4000 V JESD22-A114E 4
ESD machine model 300 V JESD22-115-A 4
ESD charged device model 2000 V 4
Latch-up 100 mA 4
Storage temperature range TSTG -65 150 C 4
Thermal resistance junction-to-ambient (10 Ld 3x3 DFN) JA 48 C/W Free air, high effective thermal conductivity test board 4
Thermal resistance junction-to-case (10 Ld 3x3 DFN) JC 4 C/W Case temperature at center of exposed metal pad 4
Thermal resistance junction-to-board at pin 3 JB 14.7 C/W Board temperature on copper trace at lead 3 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper 8. For θJB, the board temperature is taken on the board near the edge of the package, on a copper trace at either lead #3 or lead #5, as applicable. See 4

CAD (KiCad official)

  • Symbol: ISL80112IRAJZ
  • Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • 3D model: DFN-10(3x3) (KiCad packages3D, STEP)
  • 3D model files: isl80112irajz-etched.step / isl80112irajz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isl80112irajz.step / isl80112irajz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (17 pp, sha256 d613b152e8e1b270, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF