# ISL80101IRAJZ-TK

**Intersil(Renesas Electronics)** · Linear Voltage Regulators (LDO) · TDFN-10-EP(3x3)

ISL80101IRAJZ-TK from Intersil(Renesas Electronics), in a TDFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Regulated output voltage; an X5R/X7R output capacitor is required for stability. |
| 2 | VOUT | power_out | Regulated output voltage; an X5R/X7R output capacitor is required for stability. |
| 3 | ADJ | input | Connects to the feedback resistor divider to set the output voltage, and is also used by the PGOOD circuit to monitor output voltage status. |
| 4 | PG | output | Open-drain logic output indicating output voltage status (low means VOUT is not in regulation); must be grounded if not used and sink current is below 10mA. |
| 5 | GND | power_in | Ground. |
| 6 | SS | passive | External capacitor on this pin adjusts the start-up ramp and controls inrush current. |
| 7 | ENABLE | input | VIN-independent chip enable, TTL and CMOS compatible; must not be left floating and should be tied to VIN if not used. |
| 8 | NC | unconnected | No connection; leave floating. |
| 9 | VIN | power_in | Input supply (2.2V to 6V); a minimum 10µF X5R/X7R input capacitor is required. |
| 10 | VIN | power_in | Input supply (2.2V to 6V); a minimum 10µF X5R/X7R input capacitor is required. |
| 11 | EPAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Intersil(Renesas Electronics) |
| Package | TDFN-10-EP(3x3) |
| Category | Power Management ICs |
| Pins | 11 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback Pin voltage | VADJ | 491 | 500 | 509 | mV | VOUT + 0.4V < VIN < 6V, VOUT = 2.5V, 0A < ILOAD < 1A | 4 |
| DC Input Line Regulation |  | -1 |  | 1 | % | VOUT + 0.4V < VIN < 6V, VOUT = 2.5V | 4 |
| DC Output Load Regulation |  | -1 |  | 1 | % | 0A < ILOAD < 1A, VOUT = 2.5V | 4 |
| Feedback Input Current |  |  | 0.01 | 1 | µA | VADJ = 0.5V | 4 |
| Ground Pin Current | IQ |  | 3 | 5 | mA | ILOAD = 0A, VOUT + 0.4V < VIN < 6V, VOUT = 2.5V | 4 |
| Ground Pin Current | IQ |  | 5 | 7 | mA | ILOAD = 1A, VOUT + 0.4V < VIN < 6V, VOUT = 2.5V | 4 |
| Ground Pin Current in Shutdown | ISHDN |  | 0.2 | 12 | µA | ENABLE Pin = 0.2V, VIN = 6V | 4 |
| Dropout Voltage | VDO |  | 130 | 212 | mV | ILOAD = 1A, VOUT = 2.5V | 4 |
| ENABLE Turn-on Threshold |  | 0.5 | 0.8 | 1 | V |  | 5 |
| ENABLE Hysteresis |  | 10 | 80 | 200 | mV |  | 5 |
| SS Pin Current IPD | IPD | 0.5 | 1 | 1.3 | mA | VIN = 3.5V, ENABLE = 0V, SS = 1V | 5 |
| SS Pin Current ICHG | ICHG | -3.3 | -2 | -0.8 | µA | VIN = 3.5V, ENABLE = 0V, SS = 1V | 5 |
| VOUT PG Flag Threshold |  | 75 | 85 | 92 | %VOUT |  | 5 |
| ENABLE Pin Leakage Current |  |  |  | 1 | µA | VIN = 6V, ENABLE = 2.8V | 5 |
| PG Flag Low Voltage |  |  |  | 100 | mV | VIN = 3V, ISINK = 500µA | 5 |
| PG Flag Leakage Current |  |  |  | 1 | µA | VIN = 6V, PG = 6V | 5 |
| VIN Relative to GND | VIN | -0.3 |  | 6.5 | V |  | 4 |
| VOUT Relative to GND | VOUT | -0.3 |  | 6.5 | V |  | 4 |
| PG, ENABLE, ADJ, SS Relative to GND |  | -0.3 |  | 6.5 | V |  | 4 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 4 |
| Junction Temperature | TJ |  |  | 150 | °C |  | 4 |
| Junction Temperature Range | TJ | -40 |  | 125 | °C |  | 4 |
| VIN Relative to GND | VIN | 2.2 |  | 6 | V |  | 4 |
| PG, ENABLE, ADJ, SS relative to GND |  | 0 |  | 6 | V |  | 4 |
| PG Sink Current |  |  |  | 10 | mA | printed as <10mA | 4 |
| Thermal Resistance Junction-Ambient | θJA |  | 48 |  | °C/W | 10 Ld DFN Package | 4 |
| Thermal Resistance Junction-Case | θJC |  | 7 |  | °C/W | 10 Ld DFN Package | 4 |
| Output Short Circuit Current | OCP |  | 1.75 |  | A | VOUT = 0V | 4 |
| Thermal Shutdown Temperature | TSD |  | 160 |  | °C |  | 4 |
| Thermal Shutdown Hysteresis | TSDn |  | 30 |  | °C |  | 4 |
| PSRR | PSRR |  | 58 |  | dB | f = 1kHz, ILOAD = 1A; VIN = 2.2V, VOUT = 1.8V | 4 |
| PSRR | PSRR |  | 65 |  | dB | f = 120Hz, ILOAD = 1A; VIN = 2.2V, VOUT = 1.8V | 4 |
| Output Noise Voltage |  |  | 53 |  | µVRMS | ILOAD = 1A, BW = 100Hz < f < 100kHz, VIN = 2.2V, VOUT = 1.8V | 4 |
| ENABLE Pin Turn-on Delay |  |  | 100 |  | µs | COUT = 10µF, ILOAD = 1A | 5 |
| VOUT PG Flag Hysteresis |  |  | 4 |  | % |  | 5 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | COPPER |  | FIGURE 16. 3mmx3mm 10-PIN DFN ON 4-LAYER PCB WITH THERMAL VIAS JA vs EPAD-MOUNT COPPER LAND | 9 |

## CAD (KiCad official)

- Symbol: `ISL80101IRAJZ-TK`
- Footprint: `Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm`
- 3D model: TDFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `isl80101irajz-tk-etched.step` / `isl80101irajz-tk-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `isl80101irajz-tk.step` / `isl80101irajz-tk.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Intersil(Renesas Electronics) datasheet](docs/isl80101irajz-tk-datasheet.pdf) (12 pp, sha256 `0f2c70c52d37bd27`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/isl80101irajz-tk-datasheet.pdf)