component
ISL80101IRAJZ-T
Public Made by Adomby adom
RENESAS Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TDFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ISL80101IRAJZ-T
RENESAS · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TDFN-10-EP(3x3)
ISL80101IRAJZ-T from RENESAS, in a TDFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Regulated output voltage; an X5R/X7R output capacitor is required for stability. |
| 2 | VOUT | power_out | Regulated output voltage; an X5R/X7R output capacitor is required for stability. |
| 3 | ADJ | input | Feedback input from the resistor divider that sets the output voltage (0.8V to 5V); the power-good circuit also uses this pin to monitor VOUT. |
| 4 | PG | output | Open-drain power-good output that goes low when VOUT is not in regulation; it can sink up to 10mA, should not be pulled up above VIN, and must be grounded if unused. |
| 5 | GND | power_in | Ground. |
| 6 | SS | passive | External capacitor on this pin sets the start-up ramp time and controls inrush current. |
| 7 | ENABLE | input | VIN-independent chip enable, TTL and CMOS compatible; it must not be left floating and should be tied to VIN if not used. |
| 8 | NC | unconnected | No connection; leave floating. |
| 9 | VIN | power_in | Input supply, 2.2V to 6V; a minimum of 10µF X5R/X7R input capacitor is required for proper operation. |
| 10 | VIN | power_in | Input supply, 2.2V to 6V; a minimum of 10µF X5R/X7R input capacitor is required for proper operation. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | TDFN-10-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback Pin (ADJ Option Only) | VADJ | 491 | 500 | 509 | mV | VOUT + 0.4V < VIN < 6V, VOUT = 2.5V, 0A < ILOAD < 1A | 4 |
| DC Input Line Regulation | -1 | 1 | % | VOUT + 0.4V < VIN < 6V, VOUT = 2.5V | 4 | ||
| DC Output Load Regulation | -1 | 1 | % | 0A < ILOAD < 1A, VOUT = 2.5V | 4 | ||
| Feedback Input Current | 0.01 | 1 | µA | VADJ = 0.5V | 4 | ||
| Ground Pin Current (no load) | IQ | 3 | 5 | mA | ILOAD = 0A, VOUT + 0.4V < VIN < 6V, VOUT = 2.5V | 4 | |
| Ground Pin Current (1A load) | IQ | 5 | 7 | mA | ILOAD = 1A, VOUT + 0.4V < VIN < 6V, VOUT = 2.5V | 4 | |
| Ground Pin Current in Shutdown | ISHDN | 0.2 | 12 | µA | ENABLE Pin = 0.2V, VIN = 6V | 4 | |
| Dropout Voltage | VDO | 130 | 212 | mV | ILOAD = 1A, VOUT = 2.5V | 4 | |
| VOUT PG Flag Threshold | 75 | 85 | 92 | %VOUT | 5 | ||
| ENABLE Turn-on Threshold | 0.5 | 0.8 | 1 | V | 5 | ||
| ENABLE Hysteresis | 10 | 80 | 200 | mV | 5 | ||
| SS Pin Pull-down Current (discharge) | IPD | 0.5 | 1 | 1.3 | mA | VIN = 3.5V, ENABLE = 0V, SS = 1V | 5 |
| SS Pin Charge Current | ICHG | -3.3 | -2 | -0.8 | µA | 5 | |
| VIN Relative to GND (recommended) | VIN | 2.2 | 6 | V | VIN relative to GND | 4 | |
| Junction Temperature Range (recommended) | TJ | -40 | 125 | °C | Note 8 | 4 | |
| VOUT Range (minimum) | VOUT | 800 | mV | VOUT range | 4 | ||
| VOUT Range (maximum) | VOUT | 5 | V | VOUT range | 4 | ||
| PG, ENABLE, ADJ, SS Voltage Relative to GND (recommended) | 0 | 6 | V | Relative to GND | 4 | ||
| PG Sink Current | 10 | mA | Printed as <10mA | 4 | |||
| VIN Relative to GND (absolute maximum) | VIN | -0.3 | 6.5 | V | Relative to GND (Note 5) | 4 | |
| VOUT Relative to GND (absolute maximum) | VOUT | -0.3 | 6.5 | V | Relative to GND (Note 5) | 4 | |
| PG, ENABLE, ADJ, SS Relative to GND (absolute maximum) | -0.3 | 6.5 | V | Relative to GND (Note 5) | 4 | ||
| Storage Temperature Range | -65 | 150 | °C | 4 | |||
| Junction Temperature (absolute maximum) | 150 | °C | 4 | ||||
| Thermal Resistance Junction-to-Ambient, 10 Ld DFN | JA | 48 | °C/W | Free air, high effective thermal conductivity test board with direct attach (Notes 6, 7) | 4 | ||
| Thermal Resistance Junction-to-Case, 10 Ld DFN | JC | 7 | °C/W | Case temperature at center of exposed metal pad (Note 7) | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | COPPER | FIGURE 16. 3mmx3mm 10-PIN DFN ON 4-LAYER PCB WITH THERMAL VIAS JA vs EPAD-MOUNT COPPER LAND | 9 |
CAD (KiCad official)
- Symbol:
ISL80101IRAJZ-T - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: TDFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
isl80101irajz-t-etched.step/isl80101irajz-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);isl80101irajz-t.step/isl80101irajz-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (12 pp, sha256
0f2c70c52d37bd27, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ISL80101IRAJZ-T
**RENESAS** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TDFN-10-EP(3x3)
ISL80101IRAJZ-T from RENESAS, in a TDFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Regulated output voltage; an X5R/X7R output capacitor is required for stability. |
| 2 | VOUT | power_out | Regulated output voltage; an X5R/X7R output capacitor is required for stability. |
| 3 | ADJ | input | Feedback input from the resistor divider that sets the output voltage (0.8V to 5V); the power-good circuit also uses this pin to monitor VOUT. |
| 4 | PG | output | Open-drain power-good output that goes low when VOUT is not in regulation; it can sink up to 10mA, should not be pulled up above VIN, and must be grounded if unused. |
| 5 | GND | power_in | Ground. |
| 6 | SS | passive | External capacitor on this pin sets the start-up ramp time and controls inrush current. |
| 7 | ENABLE | input | VIN-independent chip enable, TTL and CMOS compatible; it must not be left floating and should be tied to VIN if not used. |
| 8 | NC | unconnected | No connection; leave floating. |
| 9 | VIN | power_in | Input supply, 2.2V to 6V; a minimum of 10µF X5R/X7R input capacitor is required for proper operation. |
| 10 | VIN | power_in | Input supply, 2.2V to 6V; a minimum of 10µF X5R/X7R input capacitor is required for proper operation. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | TDFN-10-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 11 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback Pin (ADJ Option Only) | VADJ | 491 | 500 | 509 | mV | VOUT + 0.4V < VIN < 6V, VOUT = 2.5V, 0A < ILOAD < 1A | 4 |
| DC Input Line Regulation | | -1 | | 1 | % | VOUT + 0.4V < VIN < 6V, VOUT = 2.5V | 4 |
| DC Output Load Regulation | | -1 | | 1 | % | 0A < ILOAD < 1A, VOUT = 2.5V | 4 |
| Feedback Input Current | | | 0.01 | 1 | µA | VADJ = 0.5V | 4 |
| Ground Pin Current (no load) | IQ | | 3 | 5 | mA | ILOAD = 0A, VOUT + 0.4V < VIN < 6V, VOUT = 2.5V | 4 |
| Ground Pin Current (1A load) | IQ | | 5 | 7 | mA | ILOAD = 1A, VOUT + 0.4V < VIN < 6V, VOUT = 2.5V | 4 |
| Ground Pin Current in Shutdown | ISHDN | | 0.2 | 12 | µA | ENABLE Pin = 0.2V, VIN = 6V | 4 |
| Dropout Voltage | VDO | | 130 | 212 | mV | ILOAD = 1A, VOUT = 2.5V | 4 |
| VOUT PG Flag Threshold | | 75 | 85 | 92 | %VOUT | | 5 |
| ENABLE Turn-on Threshold | | 0.5 | 0.8 | 1 | V | | 5 |
| ENABLE Hysteresis | | 10 | 80 | 200 | mV | | 5 |
| SS Pin Pull-down Current (discharge) | IPD | 0.5 | 1 | 1.3 | mA | VIN = 3.5V, ENABLE = 0V, SS = 1V | 5 |
| SS Pin Charge Current | ICHG | -3.3 | -2 | -0.8 | µA | | 5 |
| VIN Relative to GND (recommended) | VIN | 2.2 | | 6 | V | VIN relative to GND | 4 |
| Junction Temperature Range (recommended) | TJ | -40 | | 125 | °C | Note 8 | 4 |
| VOUT Range (minimum) | VOUT | 800 | | | mV | VOUT range | 4 |
| VOUT Range (maximum) | VOUT | | | 5 | V | VOUT range | 4 |
| PG, ENABLE, ADJ, SS Voltage Relative to GND (recommended) | | 0 | | 6 | V | Relative to GND | 4 |
| PG Sink Current | | | | 10 | mA | Printed as <10mA | 4 |
| VIN Relative to GND (absolute maximum) | VIN | -0.3 | | 6.5 | V | Relative to GND (Note 5) | 4 |
| VOUT Relative to GND (absolute maximum) | VOUT | -0.3 | | 6.5 | V | Relative to GND (Note 5) | 4 |
| PG, ENABLE, ADJ, SS Relative to GND (absolute maximum) | | -0.3 | | 6.5 | V | Relative to GND (Note 5) | 4 |
| Storage Temperature Range | | -65 | | 150 | °C | | 4 |
| Junction Temperature (absolute maximum) | | | | 150 | °C | | 4 |
| Thermal Resistance Junction-to-Ambient, 10 Ld DFN | JA | | 48 | | °C/W | Free air, high effective thermal conductivity test board with direct attach (Notes 6, 7) | 4 |
| Thermal Resistance Junction-to-Case, 10 Ld DFN | JC | | 7 | | °C/W | Case temperature at center of exposed metal pad (Note 7) | 4 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | COPPER | | FIGURE 16. 3mmx3mm 10-PIN DFN ON 4-LAYER PCB WITH THERMAL VIAS JA vs EPAD-MOUNT COPPER LAND | 9 |
## CAD (KiCad official)
- Symbol: `ISL80101IRAJZ-T`
- Footprint: `Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm`
- 3D model: TDFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `isl80101irajz-t-etched.step` / `isl80101irajz-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `isl80101irajz-t.step` / `isl80101irajz-t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [RENESAS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881608019886080) (12 pp, sha256 `0f2c70c52d37bd27`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/isl80101irajz-t-datasheet.pdf)