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ISL68137IRAZ

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RENESAS DC-DC Controllers, UQFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

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ISL68137IRAZ

RENESAS · DC-DC Controllers · UQFN-48-EP(6x6)

ISL68137IRAZ from RENESAS, in a UQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PWM0 output Pulse width modulation output for phase 0; connect to 3.3V logic compatible smart power stage PWM input.
2 PWM1 output Pulse width modulation output for phase 1; connect to 3.3V logic compatible smart power stage PWM input.
3 PWM2 output Pulse width modulation output for phase 2; connect to 3.3V logic compatible smart power stage PWM input.
4 PWM3 output Pulse width modulation output for phase 3; connect to 3.3V logic compatible smart power stage PWM input.
5 PWM4 output Pulse width modulation output for phase 4; connect to 3.3V logic compatible smart power stage PWM input.
6 PWM5 output Pulse width modulation output for phase 5; connect to 3.3V logic compatible smart power stage PWM input.
7 PWM6 output Pulse width modulation output for phase 6; connect to 3.3V logic compatible smart power stage PWM input.
8 AVS_CLK input AVSBus serial clock input; connect to ground if not used.
9 AVS_SDA output AVSBus serial data output; leave open if not used.
10 AVS_MDA input AVSBus master data input; connect to ground if not used.
11 AVS_VDDIO power_in AVSBus reference voltage input with range 0.90V to 3.63V; leave open if not used.
12 DNC unconnected Do not connect any signals to this pin.
13 EN0 input Active high enable input for Output 0; connect to ground if not used.
14 EN1 input Active high enable input for Output 1; connect to ground if not used.
15 TWARN output Open-drain thermal warning flag output (max pull-up VCC) asserted low on over-temperature sensed at TMON pins.
16 PG0 output Open-drain power-good indicator for Output 0 with maximum pull-up voltage VCC.
17 PG1 output Open-drain power-good indicator for Output 1 with maximum pull-up voltage VCC.
18 SCL bidirectional SMBus serial clock signal pin with maximum pull-up voltage VCC.
19 SDA bidirectional SMBus serial data signal pin with maximum pull-up voltage VCC.
20 SALRT output SMBus serial alert signal pin (open-drain output, max pull-up VCC).
21 CONFIG input Configuration ID selection pin; resistor strap selects active configuration from nonvolatile memory.
22 VINSEN input Input voltage sense pin; connect to VIN through 40.2k/10k resistor divider with 10nF decoupling capacitor.
23 VSEN1 input Positive differential voltage sense input for Output 1; connect to remote sensing point or ground if not used.
24 RGND1 input Negative differential voltage sense input for Output 1; connect to remote sensing point or ground if not used.
25 CSRTN6 input Current sense return for phase 6 forming differential pair with CS6; supports smart power stage, DCR, and resistor sensing.
26 CS6 input Current sense input for phase 6; supports smart power stage, DCR, and resistor sensing.
27 CSRTN5 input Current sense return for phase 5 forming differential pair with CS5; supports smart power stage, DCR, and resistor sensing.
28 CS5 input Current sense input for phase 5; supports smart power stage, DCR, and resistor sensing.
29 CSRTN4 input Current sense return for phase 4 forming differential pair with CS4; supports smart power stage, DCR, and resistor sensing.
30 CS4 input Current sense input for phase 4; supports smart power stage, DCR, and resistor sensing.
31 CSRTN3 input Current sense return for phase 3 forming differential pair with CS3; supports smart power stage, DCR, and resistor sensing.
32 CS3 input Current sense input for phase 3; supports smart power stage, DCR, and resistor sensing.
33 CSRTN2 input Current sense return for phase 2 forming differential pair with CS2; supports smart power stage, DCR, and resistor sensing.
34 CS2 input Current sense input for phase 2; supports smart power stage, DCR, and resistor sensing.
35 CSRTN1 input Current sense return for phase 1 forming differential pair with CS1; supports smart power stage, DCR, and resistor sensing.
36 CS1 input Current sense input for phase 1; supports smart power stage, DCR, and resistor sensing.
37 CSRTN0 input Current sense return for phase 0 forming differential pair with CS0; supports smart power stage, DCR, and resistor sensing.
38 CS0 input Current sense input for phase 0; supports smart power stage, DCR, and resistor sensing.
39 RGND0 input Negative differential voltage sense input for Output 0; connect to remote sensing point or ground if not used.
40 VSEN0 input Positive differential voltage sense input for Output 0; connect to remote sensing point or ground if not used.
41 SA input PMBus slave address selection pin; 1% resistor strap to ground determines device address per Table 2.
42 VCC power_in Chip primary +3.3V supply input; connect with high quality MLCC bypass capacitor.
43 VCCS power_out Internally generated 1.2V LDO logic supply output; decouple with 4.7µF or greater MLCC (X5R or better).
44 TMON0 input Temperature measurement input for Output 0; supports diode-based and smart power stage temperature sensing.
45 TMON1 input Temperature measurement input for Output 1; supports diode-based and smart power stage temperature sensing.
46 DNC unconnected Do not connect any signals to this pin.
47 DNC unconnected Do not connect any signals to this pin.
48 DNC unconnected Do not connect any signals to this pin.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer RENESAS
Package UQFN-48-EP(6x6)
Category Power Supply Chip
Pins 49

CAD (KiCad official)

  • Symbol: ISL68137IRAZ
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.4x4.4mm
  • 3D model: UQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: isl68137iraz-etched.step / isl68137iraz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isl68137iraz.step / isl68137iraz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (54 pp, sha256 d008d93a51c1d32d, retrieved 2026-10-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF