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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

ISL68127IRAZ-T

RENESAS · Supervisor And Reset ICs · QFN-48(6x6)

ISL68127IRAZ-T from RENESAS, in a QFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PWM6	output	PWM output for phase 6, to be connected to the 3.3V logic-compatible PWM input of a Renesas smart power stage, driver IC, or power stage.
2	PWM5	output	PWM output for phase 5, to be connected to the 3.3V logic-compatible PWM input of a Renesas smart power stage, driver IC, or power stage.
3	PWM4	output	PWM output for phase 4, to be connected to the 3.3V logic-compatible PWM input of a Renesas smart power stage, driver IC, or power stage.
4	PWM3	output	PWM output for phase 3, to be connected to the 3.3V logic-compatible PWM input of a Renesas smart power stage, driver IC, or power stage.
5	PWM2	output	PWM output for phase 2, to be connected to the 3.3V logic-compatible PWM input of a Renesas smart power stage, driver IC, or power stage.
6	PWM1	output	PWM output for phase 1, to be connected to the 3.3V logic-compatible PWM input of a Renesas smart power stage, driver IC, or power stage.
7	PWM0	output	PWM output for phase 0, to be connected to the 3.3V logic-compatible PWM input of a Renesas smart power stage, driver IC, or power stage.
8	GND	power_in	Ground pin; connect directly to a system GND plane.
9	DNC	unconnected	Do not connect any signals to this pin.
10	GND	power_in	Ground pin; connect directly to a system GND plane.
11	DNC	unconnected	Do not connect any signals to this pin.
12	DNC	unconnected	Do not connect any signals to this pin.
13	EN0	input	Active-high Output 0 enable control; connect to ground if not used.
14	EN1	input	Active-high Output 1 enable control; connect to ground if not used.
15	TWARN	output	Open-drain thermal warning flag that is pulled low without disabling the regulators on a TMON over-temperature event; maximum pull-up voltage is VCC.
16	PG0	output	Open-drain power-good indicator for Output 0; maximum pull-up voltage is VCC.
17	PG1	output	Open-drain power-good indicator for Output 1; maximum pull-up voltage is VCC.
18	SCL	bidirectional	Serial clock for the SMBus interface; maximum pull-up voltage is VCC.
19	SDA	bidirectional	Serial data for the SMBus interface; maximum pull-up voltage is VCC.
20	SALRT	output	Serial alert for the SMBus interface; maximum pull-up voltage is VCC.
21	CONFIG	input	Configuration ID selection pin, see Table 3 on page 16 for the selection details.
22	VINSEN	input	Input voltage sense; connect to VIN through a resistor divider (typically 40.2k/10k) with a 10nF decoupling capacitor.
23	VSEN1	input	Positive differential voltage sense input for Output 1; connect to a positive remote sensing point, or to ground if unused.
24	RGND1	input	Negative differential voltage sense input for Output 1; connect to a negative remote sensing point, or to ground if unused.
25	CSRTN6	input	Current sense return input of the phase 6 differential amplifier; ground it if the phase is unused.
26	CS6	input	Current sense input of the phase 6 differential amplifier; ground it if the phase is unused.
27	CSRTN5	input	Current sense return input of the phase 5 differential amplifier; ground it if the phase is unused.
28	CS5	input	Current sense input of the phase 5 differential amplifier; ground it if the phase is unused.
29	CSRTN4	input	Current sense return input of the phase 4 differential amplifier; ground it if the phase is unused.
30	CS4	input	Current sense input of the phase 4 differential amplifier; ground it if the phase is unused.
31	CSRTN3	input	Current sense return input of the phase 3 differential amplifier; ground it if the phase is unused.
32	CS3	input	Current sense input of the phase 3 differential amplifier; ground it if the phase is unused.
33	CSRTN2	input	Current sense return input of the phase 2 differential amplifier; ground it if the phase is unused.
34	CS2	input	Current sense input of the phase 2 differential amplifier; ground it if the phase is unused.
35	CSRTN1	input	Current sense return input of the phase 1 differential amplifier; ground it if the phase is unused.
36	CS1	input	Current sense input of the phase 1 differential amplifier; ground it if the phase is unused.
37	CSRTN0	input	Current sense return input of the phase 0 differential amplifier; ground it if the phase is unused.
38	CS0	input	Current sense input of the phase 0 differential amplifier; ground it if the phase is unused.
39	RGND0	input	Negative differential voltage sense input for Output 0; connect to a negative remote sensing point, or to ground if unused.
40	VSEN0	input	Positive differential voltage sense input for Output 0; connect to a positive remote sensing point, or to ground if unused.
41	SA	input	PMBus address selection pin; the resistor value sets the address per Table 2 on page 12.
42	VCC	power_in	Chip primary bias input; connect directly to a +3.3V supply with a high-quality MLCC bypass capacitor (at least 2.2µF at the pin).
43	VCCS	power_out	Internally generated 1.2V LDO logic supply derived from VCC; decouple with a 4.7µF or greater MLCC (X5R or better).
44	TMON0	input	External temperature measurement input for Output 0, supporting diode-based and smart power stage sensing; tie to ground if unused.
45	TMON1	input	External temperature measurement input for Output 1, supporting diode-based and smart power stage sensing; tie to ground if unused.
46	DNC	unconnected	Do not connect any signals to this pin.
47	DNC	unconnected	Do not connect any signals to this pin.
48	DNC	unconnected	Do not connect any signals to this pin.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	QFN-48(6x6)
Category	Power Management (PMIC)
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage VCC tolerance	VCC	-5		5	%	Nominal 3.3 V, printed as ±5%	10
Ambient Temperature		-40		85	°C		10
Output Voltage		0		3.05	V		10
VCC supply voltage (absolute maximum)	VCC			4.3	V		10
VCCS supply voltage (absolute maximum)	VCCS			1.6	V		10
All other pins voltage		-0.3			V	Referenced to GND; upper limit printed as VCC + 0.3 V	10
ESD Human Body Model				2	kV	Tested per JS-001-2014	10
ESD Charged Device Model				1	kV	Tested per JS-001-2014	10
Latch-Up				100	mA	Tested per JESD-78D; Class 2, Level A	10
Maximum Junction Temperature				150	°C		10
Maximum Storage Temperature Range		-65		150	°C		10
Enable (EN0 and EN1) Input High Level		2.55			V		10
Enable (EN0 and EN1) Input Low Level				0.8	V		10
VCCS LDO Output Voltage	VCCS	1.2	1.25	1.3	V		10
Output Voltage Adjustment Range		0.25		3.05	V		10
Output Voltage Set-Point Accuracy		-0.5		0.5	%	Set-point 0.8V to 3.05V	10
Output Voltage Set-Point Accuracy		-5		5	mV	Set-point 0.25V to <0.8V	10
Maximum Differential Input (VSEN - RGND)				3.05	V		10
Maximum Common-Mode Input (SPS mode)				1.6	V	CSRTNx - GND, SPS mode	10
Maximum Common-Mode Input (DCR mode)				3.3	V	CSRTNx - GND, DCR mode	10
Current Sense Accuracy		-2		2	%	ISEN to ADC accuracy	10
Accuracy of Switching Frequency Setting		480	500	520	kHz	When set to 500kHz	11
Switching Frequency Accuracy		-4		4	%		11
Switching Frequency Range		200		1000	kHz		11
Soft-Start Ramp Rate Accuracy		-4		4	%		11
Transition Rate Accuracy		-4		4	%		11
PWMx Output Low Level				0.4	V	IOUT = 4mA	11
Temperature Sensor Range		-50		150	°C		11
Temperature Sensor Accuracy		-4.5		4.5	%	TMON to ADC accuracy	11
TWARN Output Low Impedance		4	9	13	Ω		11
PG Output Low Voltage				0.4	V	IOUT = 8mA load	11
Input Voltage Accuracy		-2.5		2.5	%	VINSEN to ADC accuracy	11
SALERT, SDA Output Low Level				0.4	V	IOUT = 4mA	11
SCL, SDA Input High Level		1.55			V		11
SCL, SDA Input Low Level				0.8	V		11
SCL Frequency Range		0.05		2	MHz		11
Junction-to-Ambient Thermal Resistance (θJA)	θJA		27		°C/W	48 Ld 6x6 QFN, free air, high-effective thermal conductivity test board	10
Junction-to-Case Thermal Resistance (θJC)	θJC		1		°C/W	Case temp at center of exposed metal pad	10

CAD (KiCad official)

Symbol: ISL68127IRAZ-T
Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
3D model: QFN-48(6x6) (KiCad packages3D, STEP)
3D model files: isl68127iraz-t-etched.step / isl68127iraz-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isl68127iraz-t.step / isl68127iraz-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (48 pp, sha256 62cc76e4ac8da2a0, retrieved 2026-10-21, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF