ISL6722AABZ from RENESAS, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GATE	output	High current gate driver output capable of 1.0A peak source and sink, clamped to about 13.5V high level and held low when VCC is below UVLO.
2	ISENSE	input	Input to the PWM peak current sense comparator and the overcurrent comparator, whose threshold is set through ISET.
3	SYNC/SLEEP	input	On the ISL6722A this active-high logic level SLEEP input disables the IC and activates the low power standby mode.
4	SLOPE	passive	Slope compensation pin where an internal current source charges an external capacitor to GND each cycle, and the resulting ramp is added to ISENSE.
5	UV	input	Undervoltage monitor input compared to an internal 1.45V reference to detect an undervoltage condition.
6	OV	input	Overvoltage monitor input compared to an internal 2.5V reference to detect an overvoltage condition.
7	RTCT	passive	Oscillator timing pin, with resistor RT to VREF and timing capacitor CT to LGND setting a programmable frequency range of 100kHz to 1.0MHz.
8	ISET	input	A DC voltage between 0.35V and 1.2V applied to this input sets the pulse-by-pulse overcurrent threshold.
9	FB	input	Feedback voltage input connected to the inverting input of the error amplifier, whose non-inverting input is tied internally to a reference.
10	COMP	output	Output of the error amplifier and input of the PWM comparator, with the control loop compensation network connected between COMP and FB.
11	SS	passive	Soft-start capacitor connection to LGND that controls soft-start duration and overcurrent shutdown delay, with soft-start voltage clamped to 4.5V.
12	LGND	power_in	Small signal reference ground for all analog functions on the device, to be connected to PGND by a short PCB trace near the IC.
13	VREF	power_out	The 5.00V reference voltage output, to be bypassed to LGND with a 0.01µF or larger capacitor.
14	VCC	power_in	Power connection for the device, to be bypassed to LGND with a ceramic capacitor as close to the pins as possible.
15	PGND	power_in	Dedicated ground for the output gate driver, to be connected externally to LGND with a short printed circuit board trace close to the IC.
16	VC	power_in	Separate collector supply for the output gate drive, to be decoupled to PGND with a low ESR 0.1µF or larger capacitor.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	SOIC-16
Category	Power Management ICs
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
START Threshold (ISL6722A)		7.95	8.25	8.55	V	SLEEP = 0V	6
STOP Threshold		7.4	7.7	8.2	V		6
Hysteresis (ISL6722A)		0.5	0.55	1	V		6
Start-Up Current	ICC		100	175	µA	VCC < START Threshold	6
OC/OV Fault Operating Current	ICC		200	300	µA		6
Operating Current	ICC		4.5	10	mA		6
Operating Supply Current	IC		8	12	mA	Includes 1nF GATE loading	6
Reference Overall Accuracy	VREF	4.95	5	5.05	V	Line, load, TA = 0°C to +105°C	6
Reference Overall Accuracy	VREF	4.9	5	5.05	V	Line, load, TA = -40°C to +105°C	6
Reference Fault Voltage		4.5	4.65	4.75	V		6
VREF Good Voltage		4.65	4.8	4.95	V		6
Reference Hysteresis		75	165	250	mV		6
Reference Operational Current		-10			mA		6
Reference Current Limit		-20			mA		6
Current Sense Offset Voltage		0.08	0.1	0.11	V		6
Current Sense Input Voltage Range		0		1.5	V		6
Blanking Time		30	60	100	ns	Note 6	7
Gain, ACS	ACS	0.77	0.79	0.81	V/V	VSLOPE = 0V, VFB = 2.3V, VISET = 0.35V, 1.5V; ACS = ISET/ISENSE	7
Open Loop Voltage Gain		60	90		dB	Note 6	7
EA Reference Voltage Initial Accuracy		2.465	2.515	2.565	V	VFB = COMP, TA = +25°C (Note 6)	7
EA Reference Voltage		2.44	2.515	2.59	V	VFB = COMP	7
COMP to PWM Gain	ACOMP	0.31	0.33	0.35	V/V	COMP = 4V, TA = +25°C	7
COMP to PWM Offset		0.51	0.75	0.88	V	COMP = 4V	7
FB Input Bias Current		-2	0.1	2	µA	VFB = 0V	7
COMP Sink Current		2	6		mA	COMP = 1.5V, VFB = 2.7V	7
COMP Source Current		-0.25	-0.5		mA	COMP = 1.5V, VFB = 2.3V	7
COMP VOH		4.25	4.4	5	V	VFB = 2.3V	7
COMP VOL		0.4	0.8	1.2	V	VFB = 2.7V	7
PSRR		60	80		dB	Frequency = 120Hz (Note 6)	7
SS Clamp, VCOMP		2.4	2.5	2.6	V	SS = 2.5V, VFB = 0V, ISET = 2V	7
Oscillator Frequency Accuracy		289	318	347	kHz		7
Frequency Variation with VCC		-2		3	%	TA = +105°C (f20V - f9V)/f9V	7
Frequency Variation with VCC		2		3	%	TA = -40°C (f20V - f9V)/f9V	7
Maximum Duty Cycle		68	75	81	%	Note 7	7
Oscillator Discharge Current		0.75	1	1.2	mA	TA = 0°C to +105°C	7
Oscillator Discharge Current		0.7	1	1.2	mA	TA = -40°C to +105°C	7
Soft-Start Charging Current		-40	-55	-70	µA	SS = 2V	7
Charged Threshold Voltage		4.26	4.5	4.74	V		7
Initial Overcurrent Discharge Current		30	40	55	µA	Sustained OC Threshold < SS < Charged Threshold	7
Overcurrent Shutdown Threshold Voltage		0.11	0.125	0.14	V	Charged Threshold minus, TA = +25°C	7
Fault Discharge Current		0.25	1		mA	SS = 2V	7
Reset Threshold Voltage		0.22	0.27	0.31	V	TA = +25°C	7
Slope Charge Current		-45	-53	-65	µA	SLOPE = 2V, TA = 0 to +105°C	8
Slope Charge Current		-41	-53	-65	µA	SLOPE = 2V, TA = -40°C to +105°C	8
Slope Compensation Gain		0.097		0.103	V/V	Fraction of slope voltage added to ISENSE, TA = +25°C	8
Slope Compensation Gain		0.082		0.118	V/V	Fraction of slope voltage added to ISENSE (Note 4)	8
Slope Discharge Voltage			0.1	0.2	V	VRTCT = 4.5V	8
Gate Output Limit Voltage		11	13.5	16	V	VC = 20V, CGATE = 1nF, IOUT = 0mA	8
Gate VOH			1.5	2.2	V	VC - GATE, VC = 10V, IOUT = 150mA	8
Gate VOL			1.2	1.5	V	GATE - PGND, IOUT = 150mA	8
Gate VOL			0.6	0.8	V	GATE - PGND, IOUT = 10mA	8
Output Faulted Leakage		1.2	2.6		mA	VC = 20V, UV = 0V, GATE = 2V	8
Rise Time			60	100	ns	VC = 20V, CGATE = 1nF, 1V < GATE < 9V	8
Fall Time			15	40	ns	VC = 20V, CGATE = 1nF, 1V < GATE < 9V	8
Minimum ON time				110	ns	ISET = 0.5V; VFB = 0V; VC = 11V; ISENSE to GATE w/10:1 Divider; RTCT = 4.75V through 1k (Note 6)	8
Minimum ISET Voltage				0.35	V		8
Maximum ISET Voltage		1.2			V		8
ISET Bias Current		-1		1	µA	VISET = 1.00V	8
Restart Delay		150	295	445	ms	TA = +25°C	8
Overvoltage Threshold		2.4	2.5	2.6	V		8
Undervoltage Fault Threshold		1.38	1.45	1.52	V		8
Undervoltage Clear Threshold		1.41	1.53	1.62	V		8
Undervoltage Hysteresis Voltage		20	50	100	mV		8
UV Bias Current		-1		1	µA	VUV = 2.00V	8
OV Bias Current		-1		1	µA	VOV = 2.00V	8
SLEEP Input Threshold Voltage		1.4		2.7	V	Active High	8
SLEEP Input Current		11	25	46	µA	VSLEEP = 4.0V	8
ICC @ SLEEP			175	210	µA	VCC = 15V	8
Supply Voltage VCC, VC		-0.3		20	V	GND -0.3V to +20.0V	6
VREF	VREF	-0.3		5.3	V	GND - 0.3V to 5.3V	6
Peak GATE Current				1	A		6
Maximum Junction Temperature		-55		150	°C		6
Storage Temperature Range		-65		150	°C		6
Operating Temperature Range		-40		105	°C	ISL6722AAxZ	6
Supply Voltage Range (Typical)		9		18	V		6
Thermal Resistance Junction to Ambient, 16 Lead SOIC	θJA		80		°C/W	Note 1	6

CAD (KiCad official)

Symbol: ISL6722AABZ
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: isl6722aabz-etched.step / isl6722aabz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isl6722aabz.step / isl6722aabz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (26 pp, sha256 b37cf45f90023ac7, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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ISL6722AABZ

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