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Ray Publish 0.1.0 f9a3b31 17d ago

ISL6545IBZ-T

RENESAS · DC-DC Converters · SOIC-8

ISL6545IBZ-T from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BOOT power_out Provides the ground-referenced bootstrap bias for the upper MOSFET driver, equal to VCC minus the on-chip BOOT diode drop and referenced to PHASE, with VBOOT rated GND - 0.3V to 36V and VBOOT - VPHASE limited to 15V.
2 UGATE output Drives the gate of the upper MOSFET with the PWM-controlled output, and is monitored by the adaptive shoot-through protection; UGATE is rated VPHASE - 0.3V to VBOOT + 0.3V.
3 GND power_in Serves as the signal and power ground for the IC and should be tied to the ground plane through the lowest impedance connection available.
4 LGATE/OCSET output Drives the gate of the lower MOSFET from VCC and also sets the overcurrent threshold through a resistor ROCSET to GND during the short period after POR or shutdown release, with LGATE/OCSET rated GND - 0.3V to VCC + 0.3V.
5 VCC power_in Provides the bias supply for the controller, the lower gate driver and the BOOT voltage, with an operating supply of +5V ±10%, +12V ±20%, or 6.5V to 14.4V and an absolute maximum of GND - 0.3V to 15V.
6 FB input Serves as the inverting input of the internal error amplifier, with a resistor divider from the output to GND setting the regulation voltage, and is rated GND - 0.3V to 6V.
7 COMP/SD bidirectional Acts as the error amplifier output during soft-start and normal operation, and pulling it below the 0.4V nominal disable threshold shuts the controller down, with the pin rated GND - 0.3V to 6V.
8 PHASE passive Connects to the upper MOSFET source and lower MOSFET drain, serving as the UGATE driver sink and the overcurrent sense point, with PHASE rated GND - 0.3V to VBOOT + 0.3V.

Key specifications

Parameter Value
Manufacturer RENESAS
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Bias Supply Current IVCC 4 7 mA VCC = 12V; disabled 4
Rising VCC POR Threshold VPOR 3.9 4.1 4.3 V 4
VCC POR Threshold Hysteresis 0.3 0.35 0.4 V 4
Switching Frequency (ISL6545I) fOSC 240 300 330 kHz ISL6545I 4
Ramp Amplitude VOSC 1.5 VP-P 4
Reference Voltage Tolerance (ISL6545I) -1.5 1.5 % ISL6545I 4
Nominal Reference Voltage VREF 0.6 V 4
DC Gain GAIN 96 dB 4
Gain-Bandwidth Product GBWP 20 MHz 4
Slew Rate SR 9 V/µs 4
Upper Gate Source Impedance RUG-SRCh 3 VCC = 14.5V; I = 50mA 4
Upper Gate Sink Impedance RUG-SNKh 2.7 VCC = 14.5V; I = 50mA 4
Lower Gate Source Impedance RLG-SRCh 2.4 VCC = 14.5V; I = 50mA 4
Lower Gate Sink Impedance RLG-SNKh 2 VCC = 14.5V; I = 50mA 4
Upper Gate Source Impedance RUG-SRCl 3.5 VCC = 4.25V; I = 50mA 5
Upper Gate Sink Impedance RUG-SNKl 2.7 VCC = 4.25V; I = 50mA 5
Lower Gate Source Impedance RLG-SRCl 2.75 VCC = 4.25V; I = 50mA 5
Lower Gate Sink Impedance RLG-SNKl 2.1 VCC = 4.25V; I = 50mA 5
OCSET Current Source (ISL6545I) IOCSET 18 21.5 23.5 µA ISL6545I; LGATE/OCSET = 0V 5
Disable Threshold (COMP/SD pin) VDISABLE 0.375 0.4 0.425 V 5
Supply Voltage VCC 6.5 14.4 V +5V ±10%, +12V ±20%, or 6.5V to 14.4V 4
Ambient Temperature Range (ISL6545I) TA -40 85 °C ISL6545I, ISL6545AI 4
Junction Temperature Range TJ -40 125 °C 4
Supply Voltage VCC -0.3 15 V referenced to GND 4
BOOT Voltage VBOOT -0.3 36 V referenced to GND 4
Upper Driver Supply Voltage VBOOT-VPHASE 15 V 4
FB, COMP/SD Voltage VFB, VCOMP/SD -0.3 6 V referenced to GND 4
PHASE Voltage (transient) VPHASE -8 30 V GND-8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND<36V) 4
LGATE/OCSET Voltage (transient) VLGATE/OCSET -5 V GND-5V (<100ns Pulse Width, 2µJ) to VCC+0.3V 4
Human Body Model ESD HBM 1.5 kV 4
Machine Model ESD MM 150 V 4
Charged Device Model ESD CDM 1 kV 4
Maximum Junction Temperature (Plastic Package) TJ 150 °C 4
Maximum Storage Temperature Range TSTG -65 150 °C 4
Thermal Resistance JA (SOIC package) JA 95 °C/W SOIC package, mounted on high effective thermal conductivity test board in free air 4

CAD (KiCad official)

  • Symbol: ISL6545IBZ-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: isl6545ibz-t-etched.step / isl6545ibz-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isl6545ibz-t.step / isl6545ibz-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (17 pp, sha256 be5cdd01ef0fd8ea, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF