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ISL6208BCRZ-T
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RENESAS Pre-ordered Chips, DFN-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ISL6208BCRZ-T
RENESAS · Pre-ordered Chips · DFN-8-EP(2x2)
ISL6208BCRZ-T from RENESAS, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | UGATE | output | Upper gate drive output that connects to the gate of the high-side N-channel power MOSFET. |
| 2 | BOOT | power_in | Floating bootstrap supply pin for the upper gate drive, with the bootstrap capacitor connected between BOOT and PHASE (absolute maximum 33V to GND, 7V DC to PHASE). |
| 3 | PWM | input | Three-state control input for the driver that connects to the PWM output of the controller (rising threshold 1.00V typ, falling threshold 3.8V typ). |
| 4 | GND | power_in | Ground pin for the IC. |
| 5 | LGATE | output | Lower gate drive output that connects to the gate of the low-side N-channel power MOSFET. |
| 6 | VCC | power_in | Bias supply input that connects to a +5V supply (5V ±10%) with a high quality bypass capacitor to GND. |
| 7 | FCCM | input | Enables diode emulation when LOW (below 0.5V); otherwise continuous conduction mode is forced. |
| 8 | PHASE | passive | Connects to the source of the upper MOSFET and the drain of the lower MOSFET, and provides the return path for the upper gate driver. |
| 9 | THERMAL PAD | passive | Exposed thermal pad that is recommended to be connected to power ground with multiple vias for thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | DFN-8-EP(2x2) |
| Category | Interface ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| POR Rising Threshold | 3.4 | 3.9 | V | VCC Rising | 3 | ||
| POR Falling Threshold | 2.4 | 2.9 | V | VCC Falling | 3 | ||
| Bootstrap Diode Forward Voltage | VF | 0.5 | 0.55 | 0.65 | V | VVCC = 5V, forward bias current = 2mA | 3 |
| PWM Three-State Rising Threshold | 0.7 | 1 | 1.3 | V | VVCC = 5V | 3 | |
| PWM Three-State Falling Threshold | 3.5 | 3.8 | 4.1 | V | VVCC = 5V | 3 | |
| Three-State Shutdown Hold-off Time | tTSSHD | 100 | 175 | 250 | ns | VVCC = 5V, temperature = +25°C | 3 |
| FCCM LOW Threshold | 0.5 | V | 3 | ||||
| FCCM HIGH Threshold | 2 | V | 3 | ||||
| UGATE Turn-On Propagation Delay | tPDHU | 10 | 20 | 30 | ns | VVCC = 5V, outputs unloaded | 4 |
| LGATE Turn-On Propagation Delay | tPDHL | 10 | 20 | 30 | ns | VVCC = 5V, outputs unloaded | 4 |
| Upper Drive Source Resistance | RU | 1 | 2.5 | Ω | 500mA source current | 4 | |
| Upper Drive Sink Resistance | RU | 1 | 2.5 | Ω | 500mA sink current | 4 | |
| Lower Drive Source Resistance | RL | 1 | 2.5 | Ω | 500mA source current | 4 | |
| Lower Drive Sink Resistance | RL | 0.5 | 1 | Ω | 500mA sink current | 4 | |
| Supply Voltage (absolute maximum) | VCC | -0.3 | 7 | V | 3 | ||
| Input Voltage (absolute maximum) | VFCCM, VPWM | -0.3 | V | max is VCC + 0.3V | 3 | ||
| BOOT Voltage | VBOOT-GND | -0.3 | 33 | V | 3 | ||
| BOOT To PHASE Voltage | VBOOT-PHASE | -0.3 | 7 | V | DC | 3 | |
| BOOT To PHASE Voltage | VBOOT-PHASE | -0.3 | 9 | V | <10ns | 3 | |
| Ambient Temperature Range (absolute maximum) | -40 | 125 | °C | 3 | |||
| Maximum Storage Temperature Range | -65 | 150 | °C | 3 | |||
| Ambient Temperature Range (recommended) | -10 | 100 | °C | 3 | |||
| Maximum Operating Junction Temperature | 125 | °C | 3 | ||||
| Supply Voltage | VCC | -10 | 5 | 10 | % | 5V ±10% | 3 |
| Thermal Resistance Junction to Ambient, 8 Ld 2x2 DFN | θJA | 89 | °C/W | Notes 7, 8 | 3 | ||
| Thermal Resistance Junction to Case, 8 Ld 2x2 DFN | θJC | 24 | °C/W | Notes 7, 8 | 3 | ||
| Bias Supply Current | IVCC | 80 | µA | PWM pin floating, VFCCM = 5V | 3 |
CAD (KiCad official)
- Symbol:
ISL6208BCRZ-T - Footprint:
Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm - 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
isl6208bcrz-t-etched.step/isl6208bcrz-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);isl6208bcrz-t.step/isl6208bcrz-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (13 pp, sha256
f51b9c9f8f00e457, retrieved 2026-10-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ISL6208BCRZ-T
**RENESAS** · Pre-ordered Chips · DFN-8-EP(2x2)
ISL6208BCRZ-T from RENESAS, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | UGATE | output | Upper gate drive output that connects to the gate of the high-side N-channel power MOSFET. |
| 2 | BOOT | power_in | Floating bootstrap supply pin for the upper gate drive, with the bootstrap capacitor connected between BOOT and PHASE (absolute maximum 33V to GND, 7V DC to PHASE). |
| 3 | PWM | input | Three-state control input for the driver that connects to the PWM output of the controller (rising threshold 1.00V typ, falling threshold 3.8V typ). |
| 4 | GND | power_in | Ground pin for the IC. |
| 5 | LGATE | output | Lower gate drive output that connects to the gate of the low-side N-channel power MOSFET. |
| 6 | VCC | power_in | Bias supply input that connects to a +5V supply (5V ±10%) with a high quality bypass capacitor to GND. |
| 7 | FCCM | input | Enables diode emulation when LOW (below 0.5V); otherwise continuous conduction mode is forced. |
| 8 | PHASE | passive | Connects to the source of the upper MOSFET and the drain of the lower MOSFET, and provides the return path for the upper gate driver. |
| 9 | THERMAL PAD | passive | Exposed thermal pad that is recommended to be connected to power ground with multiple vias for thermal performance. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | DFN-8-EP(2x2) |
| Category | Interface ICs |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| POR Rising Threshold | | | 3.4 | 3.9 | V | VCC Rising | 3 |
| POR Falling Threshold | | 2.4 | 2.9 | | V | VCC Falling | 3 |
| Bootstrap Diode Forward Voltage | VF | 0.5 | 0.55 | 0.65 | V | VVCC = 5V, forward bias current = 2mA | 3 |
| PWM Three-State Rising Threshold | | 0.7 | 1 | 1.3 | V | VVCC = 5V | 3 |
| PWM Three-State Falling Threshold | | 3.5 | 3.8 | 4.1 | V | VVCC = 5V | 3 |
| Three-State Shutdown Hold-off Time | tTSSHD | 100 | 175 | 250 | ns | VVCC = 5V, temperature = +25°C | 3 |
| FCCM LOW Threshold | | 0.5 | | | V | | 3 |
| FCCM HIGH Threshold | | | | 2 | V | | 3 |
| UGATE Turn-On Propagation Delay | tPDHU | 10 | 20 | 30 | ns | VVCC = 5V, outputs unloaded | 4 |
| LGATE Turn-On Propagation Delay | tPDHL | 10 | 20 | 30 | ns | VVCC = 5V, outputs unloaded | 4 |
| Upper Drive Source Resistance | RU | | 1 | 2.5 | Ω | 500mA source current | 4 |
| Upper Drive Sink Resistance | RU | | 1 | 2.5 | Ω | 500mA sink current | 4 |
| Lower Drive Source Resistance | RL | | 1 | 2.5 | Ω | 500mA source current | 4 |
| Lower Drive Sink Resistance | RL | | 0.5 | 1 | Ω | 500mA sink current | 4 |
| Supply Voltage (absolute maximum) | VCC | -0.3 | | 7 | V | | 3 |
| Input Voltage (absolute maximum) | VFCCM, VPWM | -0.3 | | | V | max is VCC + 0.3V | 3 |
| BOOT Voltage | VBOOT-GND | -0.3 | | 33 | V | | 3 |
| BOOT To PHASE Voltage | VBOOT-PHASE | -0.3 | | 7 | V | DC | 3 |
| BOOT To PHASE Voltage | VBOOT-PHASE | -0.3 | | 9 | V | <10ns | 3 |
| Ambient Temperature Range (absolute maximum) | | -40 | | 125 | °C | | 3 |
| Maximum Storage Temperature Range | | -65 | | 150 | °C | | 3 |
| Ambient Temperature Range (recommended) | | -10 | | 100 | °C | | 3 |
| Maximum Operating Junction Temperature | | | | 125 | °C | | 3 |
| Supply Voltage | VCC | -10 | 5 | 10 | % | 5V ±10% | 3 |
| Thermal Resistance Junction to Ambient, 8 Ld 2x2 DFN | θJA | | 89 | | °C/W | Notes 7, 8 | 3 |
| Thermal Resistance Junction to Case, 8 Ld 2x2 DFN | θJC | | 24 | | °C/W | Notes 7, 8 | 3 |
| Bias Supply Current | IVCC | | 80 | | µA | PWM pin floating, VFCCM = 5V | 3 |
## CAD (KiCad official)
- Symbol: `ISL6208BCRZ-T`
- Footprint: `Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm`
- 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files: `isl6208bcrz-t-etched.step` / `isl6208bcrz-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `isl6208bcrz-t.step` / `isl6208bcrz-t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [RENESAS datasheet](docs/isl6208bcrz-t-datasheet.pdf) (13 pp, sha256 `f51b9c9f8f00e457`, retrieved 2026-10-26, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/isl6208bcrz-t-datasheet.pdf)