# ISL6146AFUZ

**RENESAS** · Monitors & Reset Circuits · MSOP-8

ISL6146AFUZ from RENESAS, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GATE | output | Gate drive output to the external N-channel MOSFET, generated by the internal charge pump, typically between VIN+7V at VIN=3.3V and VIN+12V at VIN=18V. |
| 2 | VIN | power_in | Sourcing-supply side sense pin at the OR-ing MOSFET source, with an operating range of 0V to 24V. |
| 3 | BIAS | power_in | Primary bias pin on the ISL6146A, which must be at least 3V and greater than VIN, with a range of 3.0 to 24V. |
| 4 | EN | input | Active high enable input for the ISL6146A that turns on the FET, internally pulled low to GND through 2MΩ, with a range of 0V to 24V. |
| 5 | GND | power_in | Chip ground reference. |
| 6 | FAULT | output | Open-drain, active-low fault output with internal on-chip filtering that is pulled to GND on a detected fault, with a range of 0 to VOUT. |
| 7 | ADJ | input | Sets the VIN-VOUT threshold of the high speed comparator; it connects directly to VOUT or through a 5kΩ to 100kΩ resistor to GND, with a range of 0.4 to VOUT. |
| 8 | VOUT | power_in | Load-side sense node connected to the OR-ing MOSFET drain and common to paralleled supplies, with a range of 0V to 24V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | MSOP-8 |
| Category | Power Management ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Bias Supply Voltage Range | BIAS | 3 |  | 20 | V |  | 6 |
| OR'd Supply Voltage Range |  | 1 |  |  | V | upper limit BIAS | 6 |
| Temperature Range (TA) | TA | -40 |  | 125 | °C |  | 6 |
| BIAS, VIN, VOUT voltage | BIAS, VIN, VOUT | -0.3 |  | 24 | V |  | 6 |
| GATE voltage | GATE | -0.3 |  | 40 | V |  | 6 |
| EN, EN, UVLO, OVP voltage | EN, EN, UVLO, OVP | -0.3 |  | 24 | V |  | 6 |
| ADJ voltage | ADJ | -0.3 |  |  | V | upper limit VOUT | 6 |
| FAULT voltage | FAULT | -0.3 |  |  | V | upper limit VOUT | 6 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 6 |
| Maximum Junction Temperature (Plastic Package) |  |  |  | 150 | °C |  | 6 |
| ESD Human Body Model |  |  |  | 2.5 | kV | Tested per JESD22-A114E | 6 |
| ESD Machine Model |  |  |  | 250 | V | Tested per JESD22-A115-A | 6 |
| Latch-up |  |  |  | 100 | mA | Tested per JESD-78B; Class 2, Level A | 6 |
| POR Rising BIAS threshold | PORL2H | 1.9 | 2.5 | 2.95 | V | BIAS Rising, GATE Rising | 6 |
| ISL6146A/B/D/E BIAS Current (enabled) | IBIAS_en_18 | 3.6 |  | 5 | mA | BIAS, VIN = 18V, ADJ, VOUT = 16.98V, enabled | 6 |
| ISL6146A VIN Current (enabled) | IVIN_en_18 | 25 |  | 40 | µA | BIAS, VIN = 18V, ADJ, VOUT = 16.98V, enabled | 6 |
| ISL6146A/B/D/E VOUT Current (enabled) | IVOUT_en_18 | 14 |  | 20 | µA | BIAS, VIN = 18V, VOUT = 16.98V, enabled | 6 |
| ISL6146A/B/D/E BIAS Current (disabled) | IBIAS_den_18 | 1.7 |  | 3 | mA | BIAS, VIN = 18V, ADJ, VOUT = 16.98V, disabled | 6 |
| ISL6146A VIN Current (disabled) | IVIN_den_18 | 27 |  | 37 | µA | BIAS, VIN = 18V, ADJ, VOUT = 16.98V, disabled | 6 |
| ISL6146A/B/D/E VOUT Current (disabled) | IVOUT_den_18 | 14 |  | 20 | µA | BIAS, VIN = 18V, VOUT = 16.98V, disabled | 6 |
| BIAS to GATE Delay | tBIAS2GTE | 150 |  | 210 | µs | BIAS > PORL2H to GATE Rising | 6 |
| Charge Pump Voltage (3V bias), above VIN | VGH_3 | 5 | 7 | 10.5 | V | VIN, BIAS = 3V; VIN - VOUT > VFWD_VR; value is VIN + x V | 6 |
| Charge Pump Voltage (12V bias), above VIN | VGH_12 | 9 | 10 | 17.5 | V | VIN, BIAS = 12V; VIN - VOUT > VFWD_VR; value is VIN + x V | 6 |
| Charge Pump Voltage (18V bias), above VIN | VGH_18 | 9 | 10 | 18 | V | VIN, BIAS = 18V; VIN - VOUT > VFWD_VR; value is VIN + x V | 6 |
| Low Voltage Level | VGL | 0 |  | 0.1 | V | VIN - VOUT < 0V | 6 |
| Low Pull-Down Current | IPDL | 5 | 8.4 | 13 | mA | VIN = 12V, VOUT = 12.2V ADJ = 11V | 6 |
| High Pull-Down Current | IPDH | 3.5 |  | 6.5 | A | VIN falling from 12V to 10V in 2µs | 6 |
| Fast Turn-off Time | ttoff | 65 |  | 130 | ns | VIN = VBIAS = 12V, VGATE = 18V to 10V, CGATE = 57nF | 6 |
| Slow Turn-off Time | ttoffs | 58 |  | 80 | µs | VIN = VBIAS = 12V, VGATE = 18V to 10V, CGATE = 57nF | 7 |
| Turn-on Current | ION |  |  | 1 | mA | BIAS = 12V, VG = 0V | 7 |
| Turn-on Current | ION |  |  | 0.15 | mA | BIAS = 12V, VG = 20V | 7 |
| GATE to VIN Rising Fault Voltage | VVG_FLTr | 320 | 440 | 560 | mV | GATE > VIN, enabled, FLT output is high | 7 |
| GATE to VIN Falling Fault Voltage | VVG_FLTf | 140 | 220 | 300 | mV | GATE > VIN, enabled, FLT output is low | 7 |
| Reverse Voltage Detection Rising VOUT Threshold | VRr | 35 | 57 | 79 | mV | VOUT rising | 7 |
| Reverse Voltage Detection Falling VOUT Threshold | VRf | 10 | 30 | 51 | mV | VOUT falling | 7 |
| Amplifier Forward Voltage Regulation | VFWD_VR | 11 | 19 | 28 | mV | ISL6146 controls voltage across FET VDS to VFWD_VR during static forward operation at loads resulting in Id*rDS(ON) < VFWD_VR | 7 |
| HS Comparator Input Offset Voltage | VOS_HS | -14 | 0.7 | 14 | mV |  | 7 |
| ADJ Adjust Threshold with 5k to GND | VTH(HS5k) | 0.57 | 0.8 | 1.1 | V | RADJ = 5kΩ to GND | 7 |
| ADJ Adjust Threshold with 100k to GND | VTH(HS100k) | 10 | 40 | 95 | mV | RADJ = 100kΩ to GND | 7 |
| VIN to VOUT Forward Fault Voltage | VFWD_FLT | 330 | 450 | 570 | mV | VIN > VOUT, GATE is fully on, FLT output is low | 7 |
| FAULT Sink Current | IFLT_SINK | 5 |  | 9 | mA | BIAS = 18V FAULT = 0.5V, VIN < VOUT, VGATE = VGL | 7 |
| FAULT Leakage Current | IFLT_LEAK | 0.04 |  | 10 | µA | FAULT = VFLT_H, VIN > VOUT, VGATE = VIN + VGQP | 7 |
| FAULT Low to High Delay | tFLT_L2H | 10 |  | 23 | µs | GATE = VGQP to FAULT output is high | 7 |
| FAULT High to Low Delay | tFLT_H2L | 1.7 |  | 3 | µs | GATE = VIN to FAULT output is low | 7 |
| ISL6146A/D EN Rising Vth | VthRa | 580 | 606 | 631 | mV |  | 7 |
| EN/UVLO Rising to GATE Rising Delay | tEN2GTER | 10 |  | 12 | µs |  | 7 |
| Thermal Resistance Junction-to-Ambient, MSOP | JA |  | 140 |  | °C/W | MSOP package, typical (Notes 4, 7) | 6 |
| Thermal Resistance Junction-to-Case, MSOP | JC |  | 41 |  | °C/W | MSOP package, typical (Notes 4, 7) | 6 |
| POR Hysteresis | PORHYS |  | 189 |  | mV |  | 6 |
| Reverse Voltage Detection Response Time | tRs |  | 10 |  | µs |  | 7 |
| VIN to VOUT Forward Fault Voltage Hysteresis | VFWD_FLT_HYS |  | 44 |  | mV | VIN > VOUT, GATE is fully on, FLT output is high | 7 |
| HS Comparator Response Time | tHSpd |  | 170 |  | ns | VOUT > VIN, 1ns transition, 5V differential | 7 |
| ISL6146A/D EN Vth Hysteresis | VthR_hysa |  | -90 |  | mV |  | 7 |

## CAD (KiCad official)

- Symbol: `ISL6146AFUZ`
- Footprint: `Package_SO:MSOP-8_3x3mm_P0.65mm`
- 3D model: MSOP-8 (KiCad packages3D, STEP)
- 3D model files: `isl6146afuz-etched.step` / `isl6146afuz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `isl6146afuz.step` / `isl6146afuz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [RENESAS datasheet](docs/isl6146afuz-datasheet.pdf) (28 pp, sha256 `5747d274e1b14869`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/isl6146afuz-datasheet.pdf)