ISL6123IRZA from RENESAS, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ENABLE	input	Input to start on/off sequencing of supplies (active-high on ISL6123); enable function is disabled for 10ms after UVLO is satisfied.
2	GATE_A	output	FET gate drive output for channel A, driving the external FET with a 1µA current source to soft-start the ramp into the load.
3	DLY_OFF_C	passive	Gate off delay timer for channel C; a capacitor to ground is charged by a 1µA source to set the turn-off delay and sequence.
4	DLY_OFF_D	passive	Gate off delay timer for channel D; a capacitor to ground is charged by a 1µA source to set the turn-off delay and sequence.
5	GATE_B	output	FET gate drive output for channel B, driving the external FET with a 1µA current source to soft-start the ramp into the load.
6	GATE_C	output	FET gate drive output for channel C, driving the external FET with a 1µA current source to soft-start the ramp into the load.
7	GATE_D	output	FET gate drive output for channel D, driving the external FET with a 1µA current source to soft-start the ramp into the load.
8	DLY_ON_B	passive	Gate on delay timer for channel B; a capacitor to ground is charged with 1µA, 10ms after turn-on is initiated, to set the turn-on delay and sequence.
9	NC	unconnected	No connect.
10	GND	power_in	Bias return; IC ground.
11	NC	unconnected	No connect (ENABLE_2 is used only on the ISL6128).
12	UVLO_B	input	Undervoltage lockout/monitoring input for channel B with a programmable threshold referenced to an internal 0.633V reference, filtered to ignore transients below 30µs.
13	DLY_OFF_B	passive	Gate off delay timer for channel B; a capacitor to ground is charged by a 1µA source to set the turn-off delay and sequence.
14	UVLO_D	input	Undervoltage lockout/monitoring input for channel D with a programmable threshold referenced to an internal 0.633V reference, filtered to ignore transients below 30µs.
15	DLY_ON_D	passive	Gate on delay timer for channel D; a capacitor to ground is charged with 1µA, 10ms after turn-on is initiated, to set the turn-on delay and sequence.
16	DLY_ON_C	passive	Gate on delay timer for channel C; a capacitor to ground is charged with 1µA, 10ms after turn-on is initiated, to set the turn-on delay and sequence.
17	UVLO_C	input	Undervoltage lockout/monitoring input for channel C with a programmable threshold referenced to an internal 0.633V reference, filtered to ignore transients below 30µs.
18	DLY_OFF_A	passive	Gate off delay timer for channel A; a capacitor to ground is charged by a 1µA source to set the turn-off delay and sequence.
19	NC	unconnected	No connect.
20	UVLO_A	input	Undervoltage lockout/monitoring input for channel A with a programmable threshold referenced to an internal 0.633V reference, filtered to ignore transients below 30µs.
21	DLY_ON_A	passive	Gate on delay timer for channel A; a capacitor to ground is charged with 1µA, 10ms after turn-on is initiated, to set the turn-on delay and sequence.
22	SYSRST	bidirectional	System reset I/O: as an input, low causes immediate unconditional latch-off of all GATE outputs; as an output, it pulls low on a UV condition, and can be tied to other ICs' SYSRST pins.
23	VDD	power_in	Chip bias; bias IC from nominal 1.5V to 5V.
24	RESET	output	Open-drain N-channel RESET output that goes high 150ms after all GATEs are fully enhanced and asserts low when UVLO is not satisfied or ENABLE is deasserted; valid for VDD down to 1V.
25	EPAD	power_in	Ground exposed pad (die substrate); can be left floating.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	QFN-24-EP(4x4)
Category	Power Management ICs
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Falling Undervoltage Lockout Threshold	VUVLOvth	619	633	647	mV	TJ = +25°C	6
Delay Charging Current	DLY_ichg	0.92	1	1.08	µA	VDLY = 0V	6
Delay Threshold Voltage	DLY_Vth	1.238	1.266	1.294	V		6
GATE Turn-On Current	IGATEon	0.8	1.1	1.4	µA	GATE = 0V	7
GATE Turn-Off Current	IGATEoff_l	-1.4	-1.05	-0.8	µA	GATE = VDD, Disabled	7
GATE High Voltage (VDD < 2V)	VGATEh	4.9			V	VDD < 2V, TJ = +25°C; printed as VDD + 4.9V	7
GATE High Voltage (VDD > 2V)	VGATEh	5		5.3	V	VDD > 2V; printed as VDD + 5V to VDD + 5.3V	7
GATE Low Voltage	VGATEl	0		0.1	V	Gate Low Voltage, VDD = 1V	7
IC Supply Current	IVDD_5V		0.2	0.5	mA	VDD = 5V	7
Undervoltage Lockout Threshold Range	RUVLOvth			7	mV	Max VUVLOvth - Min VUVLOvth	6
Delay Charging Current Range	DLY_ichg_r			0.08	µA	DLY_ichg(max) - DLY_ichg(min)	6
GATE Current Range	IGATE_range			0.35	µA	Within IC IGATE max-min	7
RESET Output Low	VRSTl			0.1	V	Measured at VDD = 5V with 5k pull-up resistors	7
SYSRST Low Output Voltage	Vol_srst			150	mV	VDD = 1.5V, IOUT = 100µA	7
VDD Supply Voltage Range	VDD	1.5		5.5	V		6
Temperature Range	TA	-40		85	°C		6
VDD Absolute Maximum	VDD			6	V	Relative to GND	6
GATE Absolute Maximum	GATE	-0.3		6	V	Printed -0.3V to VDD+6V; max is offset above VDD	6
UVLO, ENABLE, SYSRST, RESET, DLY_ON, DLY_OFF Absolute Maximum		-0.3		0.3	V	Printed -0.3V to VDD + 0.3V; max is offset above VDD	6
Maximum Junction Temperature	TJ			125	°C		6
Storage Temperature Range	Tstg	-65		150	°C		6
Thermal Resistance Junction-Ambient	θJA		46		°C/W	24 Ld 4x4 QFN, free air, Note 4	6
Thermal Resistance Junction-Case	θJC		8		°C/W	24 Ld 4x4 QFN, Note 5	6
UVLO Threshold Tempco	TCUVLOvth		40		µV/°C		6
UVLO Hysteresis	VUVLOhys		10		mV		6
UVLO Delay	TUVLOdel		10		ms	ENABLE satisfied	6
Transient Filter Duration	tFIL		30		µs	VDD, UVLO, ENABLE glitch filter	6
Delay Charging Current Temperature Coefficient	TC_DLY_ichg		0.2		nA/°C		6
Delay Threshold Voltage Temperature Coefficient	TC_DLY_Vth		0.2		mV/°C		6
ENABLE Threshold	VENh		1.2		V		6
ENABLE Threshold (relative to VDD)	VENh		0.5		xVDD	Printed 0.5 VDD	6
ENABLE Hysteresis	VENh - VENl		0.2		V	Measured at VDD = 1.5V	6
ENABLE Lockout Delay	tdelEN_LO		10		ms	UVLO satisfied	6
ENABLE Input Capacitance	Cin_en		5		pF		6
RESET Pull-Down Current	IRSTpd1		5		mA	VDD = 1.5V, RST = 0.1V	6
RESET Pull-Down Current	IRSTpd3		13		mA	VDD = 3.3V, RST = 0.1V	6
RESET Pull-Down Current	IRSTpd5		17		mA	VDD = 5V, RST = 0.1V	6
RESET Delay after GATE High	TRSTdel		160		ms	GATE = VDD+5V	7
RESET Output Capacitance	COUT_RST		10		pF		7
SYSRST Pull-Up Current	Ipu_1.5		5		µA	VDD = 1.5V	7
SYSRST Pull-Up Current	Ipu_5		100		µA	VDD = 5V	7
SYSRST Output Capacitance	Cout_srst		10		pF		7
SYSRST Low to GATE Turn-Off	tdelSYS_G		40		ns	GATE = 80% of VDD + 5V	7
GATE Turn-On/Off Current Temperature Coefficient	TC_IGATE		0.2		nA/°C		7
GATE Pull-Down High Current	IGATEoff_h		88		mA	GATE = VDD, UVLO = 0V	7
IC Supply Current	IVDD_3.3V		0.14		mA	VDD = 3.3V	7
IC Supply Current	IVDD_1.5V		0.1		mA	VDD = 1.5V	7
Stand By IC Supply Current	IVDD_sb		1		µA	VDD = 5V, ENABLE = 0V	7
VDD Power-on Reset	VDD_POR		1		V		7

CAD (KiCad official)

Symbol: ISL6123IRZA
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: isl6123irza-etched.step / isl6123irza-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isl6123irza.step / isl6123irza.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (23 pp, sha256 d52093cf8e8e8b88, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ISL6123IRZA

Verified ISL6123IRZA

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3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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